Cypress CY14B108L Specification Sheet

8 mbit (1024k x 8/512k x 16) nvsram

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Features
20 ns, 25 ns, and 45 ns Access Times
Internally organized as 1024K x 8 (CY14B108L) or 512K x 16
(CY14B108N)
Hands off Automatic STORE on power down with only a small
Capacitor
®
STORE to QuantumTrap
nonvolatile elements initiated by
Software, device pin, or AutoStore
RECALL to SRAM initiated by Software or power up
Infinite Read, Write, and RECALL Cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3V +20%, -10% operation
Commercial and Industrial Temperatures
48-ball FBGA and 44-pin and 54-pin TSOP-II packages
Pb-free and RoHS compliant
Logic Block Diagram
Note
1. Address A
- A
for x8 configuration and Address A
0
19
2. Data DQ
- DQ
for x8 configuration and Data DQ
0
7
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-45523 Rev. *B
PRELIMINARY
8 Mbit (1024K x 8/512K x 16) nvSRAM
®
on power down
[1, 2, 3]
A
R
0
A
O
1
A
W
2
A
3
A
D
4
E
A
5
C
A
6
O
A
7
D
A
8
E
A
17
R
A
18
A
19
DQ
0
DQ
1
DQ
2
DQ
3
I
DQ
4
N
DQ
P
5
U
DQ
6
T
DQ
B
7
U
DQ
8
F
DQ
F
9
E
DQ
10
R
DQ
S
11
DQ
12
DQ
13
DQ
14
A
9
DQ
15
- A
for x16 configuration.
0
18
- DQ
for x16 configuration.
0
15
198 Champion Court

Functional Description

The Cypress CY14B108L/CY14B108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 1024 Kbytes of 8 bits each or 512K words of 16 bits
each.
The
embedded
QuantumTrap technology, producing the world's most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
V
CC
Quatrum Trap
2048 X 2048 X 2
POWER
CONTROL
STORE
RECALL
STORE/RECALL
CONTROL
STATIC RAM
ARRAY
2048 X 2048 X 2
SOFTWARE
DETECT
COLUMN I/O
COLUMN DEC
A
A
A
A
A
A
A
10
11
12
13
14
15
16
San Jose
CY14B108L, CY14B108N
nonvolatile
elements
V
CAP
HSB
A
- A
14
2
OE
WE
CE
BLE
BHE
,
CA 95134-1709
408-943-2600
Revised March 19, 2009
incorporate
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Summary of Contents for Cypress CY14B108L

  • Page 1: Functional Description

    Features 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 1024K x 8 (CY14B108L) or 512K x 16 ■ (CY14B108N) Hands off Automatic STORE on power down with only a small ■ Capacitor ® STORE to QuantumTrap nonvolatile elements initiated by ■...
  • Page 2 4. Address expansion for 16 Mbit. NC pin not connected to die. Document #: 001-45523 Rev. *B PRELIMINARY Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44/54-Pin TSOP II CY14B108L, CY14B108N 48-FBGA (x16) Top View (not to scale)
  • Page 3 Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect No Connect. This pin is not connected to the die. Document #: 001-45523 Rev. *B PRELIMINARY Description - DQ - DQ CY14B108L, CY14B108N Page 3 of 24 [+] Feedback...
  • Page 4: Device Operation

    HIGH. In case the write latch is not set, HSB is not driven pin. This stored LOW by the CY14B108L/CY14B108N. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or , the part other external source.
  • Page 5 STORE operation is completed, the CY14B108L/CY14B108N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power Up) During power after < V ), an internal RECALL request is latched. When...
  • Page 6 OE, BHE, BLE Notes 5. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A Rest of the address lines are don’t care. 6. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
  • Page 7: Data Protection

    AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. Data Protection The CY14B108L/CY14B108N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when V <...
  • Page 8: Maximum Ratings

    < V < V , CE or OE > V = –2 mA = 4 mA pin and V , 5V Rated CY14B108L, CY14B108N + 2.0V = 25°C) ...1.0W Ambient Temperature 0°C to +70°C 2.7V to 3.6V –40°C to +85°C 2.7V to 3.6V...
  • Page 9: Thermal Resistance

    Test Conditions = 25°C, f = 1 MHz, = 0 to 3.0V [10] Test Conditions Figure 4. AC Test Loads 3.0V OUTPUT 5 pF 789 Ω CY14B108L, CY14B108N Unit Years Unit 48-FBGA 44-TSOP II 54-TSOP II Unit °C/W 28.82 31.11 30.73 °C/W...
  • Page 10: Switching Waveforms

    14. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 15. HSB must remain HIGH during READ and WRITE cycles. Document #: 001-45523 Rev. *B PRELIMINARY 20 ns Description Address Valid CY14B108L, CY14B108N 25 ns 45 ns Unit [11, 12, 15] Output Data Valid Page 10 of 24...
  • Page 11 16. CE or WE must be >V during address transitions. Document #: 001-45523 Rev. *B PRELIMINARY Address Valid LZCE LZOE LZBE Output Data Valid Active [3, 14, 15, 16] CY14B108L, CY14B108N [3, 11, 15] HZCE HZOE HZBE Page 11 of 24 [+] Feedback...
  • Page 12 Data Input Data Output Document #: 001-45523 Rev. *B PRELIMINARY [3, 14, 15, 16] Address Valid Input Data Valid High Impedance Address Valid Input Data Valid High Impedance CY14B108L, CY14B108N [3, 14, 15, 16] Page 12 of 24 [+] Feedback...
  • Page 13 Figure 10. AutoStore or Power Up RECALL Note STORE HHHD LZHSB DELAY HRECALL Read & Write BROWN POWER-UP RECALL Autostore SWITCH. is below V SWITCH. CY14B108L, CY14B108N 25 ns 45 ns 2.65 2.65 [20] Note STORE Note HHHD DELAY LZHSB HRECALL Read & Write POWER...
  • Page 14 Address #6 DELAY HZCE Figure 12. Autostore Enable/Disable Cycle Address #6 HZCE Table 2 on page 6. WE must be HIGH during all six consecutive cycles. CY14B108L, CY14B108N [22, 23] 25 ns 45 ns [23] HHHD LZHSB High Impedance STORE...
  • Page 15 SRAM is disabled as long as HSB (IN) is driven low. DHSB DHSB [24, 25] Figure 14. Soft Sequence Processing Soft Sequence Command Address #6 Address #1 CY14B108L, CY14B108N 25 ns 45 ns Unit μs HHHD LZHSB only by Internal Address #6...
  • Page 16 High-Z Output Disabled Data In (DQ –DQ Write Data In (DQ –DQ Write –DQ in High-Z Data In (DQ –DQ Write –DQ in High-Z CY14B108L, CY14B108N Mode Power Standby Active Active Active Mode Power Standby Active Active Active Active Active...
  • Page 17: Ordering Information

    51-85128 48-ball FBGA 51-85128 48-ball FBGA 51-85128 48-ball FBGA 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II CY14B108L, CY14B108N Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial...
  • Page 18 51-85128 48-ball FBGA 51-85128 48-ball FBGA 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II CY14B108L, CY14B108N Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 18 of 24 [+] Feedback...
  • Page 19: Part Numbering Nomenclature

    C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Package: BA - 48 FBGA ZS - TSOP II Voltage: B - 3.0V CY14B108L, CY14B108N Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns Data Bus: L - x8...
  • Page 20: Package Diagrams

    Figure 15. 44-Pin TSOP II (51-85087) PIN 1 I.D. BASE PLANE 0°-5° 0.10 (.004) 0.597 (0.0235) 0.406 (0.0160) SEATING PLANE CY14B108L, CY14B108N DIMENSION IN MM (INCH) MIN. EJECTOR PIN BOTTOM VIEW 10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047) 51-85087-*A...
  • Page 21 Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128) TOP VIEW A1 CORNER 6.00±0.10 SEATING PLANE Document #: 001-45523 Rev. *B PRELIMINARY CY14B108L, CY14B108N BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) 1.875 0.75...
  • Page 22 PRELIMINARY CY14B108L, CY14B108N Package Diagrams (continued) Figure 17. 54-Pin TSOP II (51-85160) 51-85160-** Document #: 001-45523 Rev. *B Page 22 of 24 [+] Feedback...
  • Page 23 Document History Page Document Title: CY14B108L/CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001-45523 Submission Rev. ECN No. Orig. of Change 2428826 GVCH See ECN 2520023 GVCH/PYRS 06/23/08 2676670 GVCH/PYRS 03/20/2009 Document #: 001-45523 Rev. *B PRELIMINARY...
  • Page 24 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. PRELIMINARY PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b Revised March 19, 2009 CY14B108L, CY14B108N psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page 24 of 24 [+] Feedback...

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