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Cypress CY14B101Q1 Specification Sheet

1 mbit (128k x 8) serial spi nvsram
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Features
1 Mbit NonVolatile SRAM
■
Internally organized as 128K x 8
❐
STORE to QuantumTrap
❐
tomatically on power down (AutoStore
HSB pin (Hardware Store) or SPI instruction (Software Store)
RECALL to SRAM initiated on power up (Power Up Recall
❐
or by SPI Instruction (Software RECALL)
Automatic STORE on power down with a small capacitor
❐
High Reliability
■
Infinite Read, Write, and RECALLl cycles
❐
200,000 STORE cycles to QuantumTrap
❐
Data Retention: 20 Years
❐
High Speed Serial Peripheral Interface (SPI)
■
40 MHz Clock rate
❐
Supports SPI Modes 0 (0,0) and 3 (1,1)
❐
Write Protection
■
Hardware Protection using Write Protect (WP) Pin
❐
Software Protection using Write Disable Instruction
❐
Software Block Protection for 1/4,1/2, or entire Array
❐
Logic Block Diagram
CS
WP
SCK
HOLD
SI
Cypress Semiconductor Corporation
Document #: 001-50091 Rev. *A
PRELIMINARY
1 Mbit (128K x 8) Serial SPI nvSRAM
®
nonvolatile elements initiated au-
®
) or by user using
Instruction decode
Write protect
Control logic
Instruction
register
A0-A16
Address
Decoder
•
198 Champion Court
Low Power Consumption
■
Single 3V +20%, –10% operation
❐
Average Vcc current of 10 mA at 40 MHz operation
❐
Industry Standard Configurations
■
Commercial and industrial temperatures
❐
CY14B101Q1 has identical pin configuration to industry stan-
❐
dard 8-pin NV Memory
®
)
8-pin DFN and 16-pin SOIC Packages
❐
RoHS compliant
❐

Functional Overview

The
Cypress
CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nonvolatile static RAM with a nonvolatile
element in each memory cell. The memory is organized as 128K
words of 8 bits each. The embedded nonvolatile elements incor-
porate the QuantumTrap technology, creating the world's most
reliable nonvolatile memory. The SRAM provides infinite read
and write cycles, while the QuantumTrap cell provides highly
reliable nonvolatile storage of data. Data transfers from SRAM to
the nonvolatile elements (STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
Both STORE and RECALL operations can also be triggered by
the user.
Quantum Trap
128K X 8
STORE
SRAM ARRAY
RECALL
128K X 8
D0-D7
Data I/O register
Status register
,
•
San Jose
CA 95134-1709
CY14B101Q1
CY14B101Q2
CY14B101Q3
V
V
CC
CAP
Power Control
STORE/RECALL
HSB
Control
SO
•
408-943-2600
Revised February 2, 2009
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Summary of Contents for Cypress CY14B101Q1

  • Page 1: Functional Overview

    ❐ Industry Standard Configurations ■ Commercial and industrial temperatures ® ❐ ) or by user using CY14B101Q1 has identical pin configuration to industry stan- ❐ dard 8-pin NV Memory ® 8-pin DFN and 16-pin SOIC Packages ❐ RoHS compliant ❐...
  • Page 2 Pinouts CY14B101Q1 Top View not to scale Table 1. Pin Definitions Pin Name I/O Type Input Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low power standby mode. Input Serial Clock. Runs at speeds up to max 40 MHz. All inputs are latched at the rising edge of this clock.

  • Page 3: Device Operation

    Device Operation CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM memory with a nonvolatile element in each memory cell. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence which transfers the data in parallel to the nonvolatile Quantum Trap cells.
  • Page 4 HSB pin returns HIGH. Leave the HSB pin unconnected if not used. Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY bit of the SPI status register may be probed to determine the Ready or Busy status of nvSRAM Document #: 001-50091 Rev.

  • Page 5: Serial Peripheral Interface

    In CY14B101Q1, V pin is not present and AutoStore option is not available. The Autostore Enable and Disable instructions to CY14B101Q1 are ignored. Note If AutoStore is disabled and V open. V pin must never be connected to GND. Power Up Recall operation cannot be disabled in any case.

  • Page 6: Spi Modes

    Figure 4. System Configuration Using SPI nvSRAM u C o n tro lle r SPI Modes CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: SPI Mode 0 (CPOL=0, CPHA=0) ■...

  • Page 7: Spi Functional Description

    RECALL cycle is completed. In the Standby Power mode, the current drawn by the device drops to I SPI Functional Description The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit instruction register. Instructions and their opcodes are listed in Table 3. All instructions, addresses, and data are transferred with the MSB first and start with a HIGH to LOW CS transition.

  • Page 8: Status Register

    Status Register are saved to nonvolatile memory only after a STORE operation. If AutoStore is disabled (or while using CY14B101Q1), any modifications to the Status Register must be secured by using a Software STORE operation Note CY14B101Q2 does not have WP pin. Any modification to bit 7 of the Status register has no effect on the functionality of CY14B101Q2.
  • Page 9 Figure 8. Write Status Register (WRSR) Instruction Timing Write Protection and Block Protection CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features for both software and hardware write protection using WRDI instruction and WP. Additionally, this device also provides block protection mechanism through BP0 and BP1 pins of the Status Register.

  • Page 10: Memory Access

    SCK. Any other data on SI line after the last address bit is ignored. CY14B101Q1/CY14B101Q2/CY14B101Q3 allows reads to be performed in bursts through SPI which can be used to read consecutive addresses without issuing a new READ instruction.
  • Page 11 Figure 12. Burst Mode Read Instruction Timing Op-Code Op-Code Figure 14. Burst Mode Write Instruction Timing Op-Code nvSRAM Special Instructions CY14B101Q1/CY14B101Q2/CY14B101Q3 special instructions which enables access to four nvSRAM specific functions: STORE, RECALL, ASDISB, and ASENB. Table 8 lists these instructions. Software STORE When a STORE instruction is executed, nvSRAM performs a Software STORE operation.
  • Page 12 AutoStore Enable (ASENB) The AutoStore Enable instruction enables the AutoStore on CY14B101Q1. This setting is not nonvolatile and needs to be followed by a STORE sequence to survive the power cycle. To issue this instruction, the device must be write enabled (WEN = ‘1’).

  • Page 13: Maximum Ratings

    < V = Max, V < V < V = –2 mA = 4 mA pin and V , 5V Rated CY14B101Q1 CY14B101Q2 CY14B101Q3 + 2.0V = 25°C) ... 1.0W Ambient Temperature 0°C to +70°C 2.7V to 3.6V –40°C to +85°C 2.7V to 3.6V...

  • Page 14: Thermal Resistance

    = 3.0V Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. Figure 20. AC Test Loads and Waveforms 577Ω 3.0V OUTPUT 789Ω CY14B101Q1 CY14B101Q2 CY14B101Q3 Unit Years Unit 8-SOIC 8-DFN Unit °C/W °C/W...
  • Page 15 Figure 21. Synchronous Data Timing (Mode 0) t CH t CL t HD t CO Figure 22. HOLD Timing t HH t SH t SH t HHZ CY14B101Q1 CY14B101Q2 CY14B101Q3 40MHz Unit t CS t CSH t HZCS t OH HI-Z...

  • Page 16: Switching Waveforms

    Note 8 t STORE t HHHD t LZHSB t DELAY t FA t FA Read and Write BROWN POWER-UP RECALL AUTOSTORE SWITCH. CY14B101Q1 CY14B101Q2 CY14B101Q3 CY‘4B101QxA 2.65 [10] Note 8 t STORE Note 11 t HHHD t DELAY t LZHSB POWER...
  • Page 17 13. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command. Document #: 001-50091 Rev. *A PRELIMINARY Description [12] Figure 24. Software STORE Cycle t STORE Hi-Z [12] Figure 25. Software RECALL Cycle t RECALL Hi-Z CY14B101Q1 CY14B101Q2 CY14B101Q3 CY14B101Q1 Unit μs μs Page 17 of 22 [+] Feedback...
  • Page 18 STORE HSB pin is driven high to V CC only by Internal 100K resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. t DHSB t DHSB CY14B101Q1 CY14B101Q2 CY14B101Q3 CY14B101Q1 Unit t HHHD...

  • Page 19: Ordering Information

    Ordering Information Ordering Code CY14B101Q1-LHXIT CY14B101Q1-LHXI CY14B101Q1-LHXCT CY14B101Q1-LHXC CY14B101Q2-LHXIT CY14B101Q2-LHXI CY14B101Q2-LHXCT CY14B101Q2-LHXC CY14B101Q3-SFXIT CY14B101Q3-SFXI CY14B101Q3-SFXCT CY14B101Q3-SFXC All the above parts are Pb - free. The above table contains advance information. Contact your local Cypress sales representative for availability of these parts.

  • Page 20: Package Diagrams

    NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS 2. PACKAGE WEIGHT: TBD 3. BASED ON REF JEDEC # MO-240 EXCEPT DIMENSIONS (L) and (b) Document #: 001-50091 Rev. *A PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 001-50671 *A Page 20 of 22 [+] Feedback...
  • Page 21 Package Diagrams (continued) Document #: 001-50091 Rev. *A PRELIMINARY Figure 28. 16-Pin (300 mil) SOIC (51-85022) CY14B101Q1 CY14B101Q2 CY14B101Q3 51-85022 *B Page 21 of 22 [+] Feedback...
  • Page 22 Document History Page Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3 1 MBit (128K x 8) Serial SPI nvSRAM Document Number: 001-50091 Orig. of Submission REV. ECN NO. Change 2607408 GSIN/ 12/19/08 GVCH/AESA 2654487 GVCH/PYRS 02/04/2009 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.

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