Cypress CY14E256L Specification Sheet

256 kbit (32k x 8) nvsram

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Features
25 ns, 35 ns, and 45 ns access times
Pin compatible with STK14C88
Hands off automatic STORE on power down with external 68
µF capacitor
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
RECALL to SRAM initiated by software or power up
Unlimited READ, WRITE, and RECALL cycles
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5V+10% operation
Commercial and industrial temperature
32-pin SOIC and CDIP (300 mil) packages
RoHS compliance
Logic Block Diagram
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Cypress Semiconductor Corporation
Document Number: 001-06968 Rev. *F

Functional Description

The Cypress CY14E256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world's most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
Quantum Trap
512 X 512
STORE
RECALL
STATIC RAM
ARRAY
512 X 512
COLUMN I/O
COLUMN DEC
A
A
A
A
A
A
0
1
2
3
4
10
198 Champion Court
256 Kbit (32K x 8) nvSRAM
V
V
CC
CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
,
San Jose
CA 95134-1709
CY14E256L
HSB
-
A
A
13
0
OE
CE
WE
408-943-2600
Revised January 30, 2009
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Summary of Contents for Cypress CY14E256L

  • Page 1: Functional Description

    Document Number: 001-06968 Rev. *F 256 Kbit (32K x 8) nvSRAM Functional Description The Cypress CY14E256L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell.
  • Page 2: Pin Configurations

    (connection optional). Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Document Number: 001-06968 Rev. *F Figure 1. Pin Diagram: 32-Pin SOIC/DIP Description CY14E256L Page 2 of 18 [+] Feedback...
  • Page 3: Device Operation

    Device Operation The CY14E256L nvSRAM is made up of two functional compo- nents paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the...
  • Page 4 Document Number: 001-06968 Rev. *F If the CY14E256L is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE...
  • Page 5: Noise Considerations

    CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations The CY14E256L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between V...
  • Page 6: Best Practices

    4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. 5. While there are 15 addresses on the CY14E256L, only the lower 14 are used to control software modes.
  • Page 7: Maximum Ratings

    < V < V , CE or OE > V = –4 mA if that is where the power supply connection is made, or V CY14E256L Ambient Temperature 0°C to +70°C 4.5V to 5.5V -40°C to +85°C 4.5V to 5.5V...
  • Page 8: Thermal Resistance

    = 0 to 3.0V Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. Figure 6. AC Test Loads 5.0V Output 5 pF 512Ω CY14E256L Unit Unit Years 1,000 Unit 32-SOIC 32-CDIP Unit °C/W 35.45...
  • Page 9: Switching Waveforms

    10. Device is continuously selected with CE and OE both Low. 11. Measured ±200 mV from steady state output voltage. Document Number: 001-06968 Rev. *F 25 ns Description CY14E256L 35 ns 45 ns Unit [9, 10] Page 9 of 18...
  • Page 10 14. CE or WE must be greater than V during address transitions. Document Number: 001-06968 Rev. *F 25 ns Description [13, 14] DATA VALID HZWE HIGH IMPEDANCE [13, 14] DATA VALID HIGH IMPEDANCE CY14E256L 35 ns 45 ns Unit LZWE Page 10 of 18 [+] Feedback...
  • Page 11 ) to HSB low SWITCH Figure 11. AutoStore/Power Up RECALL SWITCH . If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB is released and no store SWITCH CY14E256L CY14E256L Unit μs μs μs Page 11 of 18...
  • Page 12 19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. Document Number: 001-06968 Rev. *F [19] 25 ns Description DATA VALID CY14E256L 35 ns 45 ns Unit [19] STORE...
  • Page 13 Hardware STORE Low to STORE Busy HLBL Switching Waveforms Note 20. t is only applicable after t is complete. DHSB STORE Document Number: 001-06968 Rev. *F Description Figure 13. Hardware STORE Cycle CY14E256L CY14E256L Unit Page 13 of 18 [+] Feedback...
  • Page 14: Ordering Information

    Part Numbering Nomenclature (Commercial and Industrial) CY 14 E 256 L- SZ 25 X C T Pb-Free nvSRAM 14 - AutoStore + Software Store + Hardware Store Cypress Ordering Information Speed Ordering Code (ns) CY14E256L-SZ25XCT CY14E256L-SZ25XC CY14E256L-SZ25XIT CY14E256L-SZ25XI CY14E256L-SZ35XCT CY14E256L-SZ35XC CY14E256L-SZ35XIT CY14E256L-SZ35XI CY14E256L-SZ45XCT CY14E256L-SZ45XC...
  • Page 15: Package Diagram

    0.292[7.416] 0.299[7.594] REFERENCE JEDEC MO-119 0.405[10.287] 0.419[10.642] SEATING PLANE 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] CY14E256L MIN. MAX. PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. 51-85058 *A 0.006[0.152] 0.021[0.533] 0.012[0.304] 0.041[1.041] 51-85127-*A Page 15 of 18 [+] Feedback...
  • Page 16 CY14E256L Package Diagram (continued) Figure 15. 32-Pin (300 Mil) CDIP (001-51694) 001-51694 ** Document Number: 001-06968 Rev. *F Page 16 of 18 [+] Feedback...
  • Page 17 Document History Page Document Title: CY14E256L 256 Kbit (32K x 8) nvSRAM Document Number: 001-06968 Submission Rev. ECN No. Date 427789 See ECN 437321 See ECN 472053 See ECN 503290 See ECN 1349963 See ECN 2427986 See ECN 2606744 02/19/09 Document Number: 001-06968 Rev.
  • Page 18 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b Revised January 30, 2009 CY14E256L psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page 18 of 18 [+] Feedback...

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