Cypress CY91590 Series Hardware Manual

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Summary of Contents for Cypress CY91590 Series

Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
Page 2 CY91590 Series FR81S Hardware Manual Document Number: 002-05526 Rev. *B Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 www.cypress.com...
Page 3 Cypress product as a Critical Component in a High- Risk Device.
Page 4 Cypress offers sample programs free of charge for using the peripheral functions of the FR81S family. Cypress also makes available descriptions of the development environment required for the CY91590 series. Feel free to use them to verify the operational specifications and usage of this Cypress microcontroller.
Page 5 This manual uses the following terminology. Term Explanation Word Indicates access in units of 32 bits. Half word Indicates access in units of 16 bits. Byte Indicates access in units of 8 bits. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 6 During the oscillation stabilization wait time, the clock is not supplied. wait time The on-chip debugger for this series OCDU The OCD interface built in this product. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 7 B, H, W UART0 00001000 B, H, W 00000100 00000-0- XXXXXXXX DRCL0[W] UTIMC0[R/W] UTIM0[R] H XXXXXXX 0--00001 000064 (UTIMR0[W]H) U-TIMER0 00000000 00000000 Initial Value Write only Byte access, Half-word access, Word access CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 8 Therefore, if the SSR0 register is set to the Half-word access, for example, SSR0 + SIDR0 (SODR0) register at address 060 is accessed. (If the address offsets are +1 and +2 (for example, SIDR0+SCR0), the Half-word access is not allowed.) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 9 Access size Address Bit position Word Half-word Word Bit name If the address offset is +3: (Example of SMR0 register) Access size Address Bit position Word Half-word Word Bit name SCKE CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 10 : Undefined bit (The read value is undefined. Writing has no effect on operation.)  R0,WX : Undefined bit (The read value is "0". Writing has no effect on operation.) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 11: Table Of Contents
1.10.20 Pins of GDC (Capture 656 Mode) ......................126 1.10.21 Pins of GDC (Capture Other) ........................ 127 1.10.22 Pins of GDC (Display) ........................... 128 1.10.23 Pins of GDC (NTSC) ..........................130 1.10.24 Pin of GDC (HS-SPI) ..........................131 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 12 Registers ................................218 5.4.1 Division Configuration Register 0 : DIVR0 (Division clock configuration Register 0) ......219 5.4.2 Division Configuration Register 1 : DIVR1 (Division clock configuration Register 1) ......220 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 13 Timer ..............................295 5.5.5 Notes when Clocks Conflict ........................303 5.5.6 The Clock Gear Circuit ......................... 304 5.5.7 Operations during MDI Communications ....................307 5.5.8 About PMU clock (PMUCLK) ........................ 308 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 14 DMA Operation Enable ......................... 392 8.5.2 Separate Items for Each Channel ......................393 8.5.3 Operations ............................397 DMA Usage Examples ............................409 Generation and Clearing of DMA Transfer Requests ..................... 411 Overview ................................412 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 15 (Port Function Register 00-13,A-H) ...................... 460 11.4.4 Input Data Direct Register 00 to 13, A to H : PDDR00 to PDDR13, PDDRA to PDDRH (Port Data Direct Register 00-13,A-H) ....................462 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 16 13.4.3 External Interrupt Request Level Register 0/1 : ELVR0/ELVR1 (External interrupt LeVel Register 0/1)542 13.5 Operation ................................543 13.6 Setting ................................546 13.7 Q&A ................................... 547 13.8 Notes ................................. 548 14. NMI Input ..................................549 14.1 Overview ................................550 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 17 16.4.15 Interrupt Request Batch Read Register 7 upper-order : IRPR7H (Interrupt Request Peripheral Read register 7H) .................. 585 16.4.16 Interrupt Request Batch Read Register 7 lower-order : IRPR7L (Interrupt Request Peripheral Read register 7L) ................... 586 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 18 17.4.8 PPG0 Output Division Setting Register : PPGDIV ................622 17.5 Operation ................................623 17.5.1 PWM Operation ............................ 624 17.5.2 One-shot Operation ..........................626 17.5.3 Restart Operation ..........................628 17.6 Setting ................................629 17.7 Q&A ................................... 631 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 19 19.4.4 Registers for 16-bit PPG Timer ......................696 19.4.5 16/32-bit PWC Timer Register ......................700 19.5 Operation ................................704 19.5.1 Selection of Timer Function ........................705 19.5.2 I/O Allocation ............................706 19.5.3 32-bit Mode Operation .......................... 709 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 20 21.7.2 How to Select the External Clock......................854 21.7.3 How to Enable/Disable the Count Operation of the Free-run Timer ............. 855 21.7.4 How to Clear the Free-run Timer ......................856 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 21 23.4.4 LIN SYNCH FIELD Switching Register : LSYNS .................. 912 23.5 Operation ................................914 23.5.1 Capture and Interrupt Timings ......................915 23.5.2 Edge Detection Specifications for Input Capture And Their Operations ..........917 23.6 Setting ................................919 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 22 25.4.6 Main Oscillation Timer Result Register 1 : CUTR1 (Calibration Unit Timer Result register 1) ....969 25.4.7 CR Oscillation Trimming Setting Register : CRTR (CR oscillator calibration Trimming Register) ..970 25.5 Operation ................................971 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 23 27.5.2 Internal Low-voltage Detection in GDC unit ..................1030 27.6 Notes ................................1031 28. Low Voltage Detection (External Low-Voltage Detection) ................... 1033 28.1 Overview ................................. 1034 28.2 Features ................................1035 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 24 31.4.2 Sound Control Register: SGCR (SG Control Register) ............... 1085 31.4.3 Amplitude Data Register : SGAR (SG Amplitude Register) ..............1088 31.4.4 Frequency Data Register : SGFR (SG Frequency Register) .............. 1089 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 25 33.2 Features ................................1155 33.3 Configuration ..............................1156 33.4 Register ................................1157 33.4.1 Regulator Output Voltage Select Register : REGSEL (REGulator output voltage SELect register) ..1158 33.5 Operation ................................. 1160 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 26 36.4.5 ECC False Error Generation Control Register XBS RAM : EFECRX ( Ecc False Error Control Register Xbs ram) ..................1214 36.4.6 ECC Error Control Register AHB RAM : EECSRH (Ecc Error Control and Status Register aHb ram) 1216 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 27 37.6.2 Operation of CSIO ..........................1350 37.6.3 Setup Procedure and Program Flow ....................1371 37.7 Operation of LIN-UART ........................... 1375 37.7.1 Interrupts of LIN-UART ........................1376 37.7.2 Operation of LIN-UART ........................1386 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 28 38.8 Notes on Usage ............................... 1613 38.8.1 Operation Enable ..........................1614 38.8.2 Communication Mode Setting ......................1615 38.8.3 Timing of Enabling Transmission Interrupt ..................1616 38.8.4 Operation Setting Change ........................1617 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 29 40.4.5 Conversion Time Setting Register: ADCT ..................1735 40.4.6 A/D Start/Completion Channel Setting Register : ADSCH, ADECH ........... 1737 40.5 Operation ................................. 1740 40.5.1 Single Conversion Operation ......................1741 40.5.2 Scan Conversion Operation ........................ 1742 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 30 41.5.8 Sector Erase Suspend Command ...................... 1812 41.5.9 Security Function ..........................1813 41.5.10 Notes on Using Flash Memory ......................1818 42. WorkFlash Memory ..............................1819 42.1 Overview ................................. 1820 42.2 Features ................................1821 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 31 44.4.3 GDC Swap Setting Register : GDCSWPR ..................1895 44.5 Note ................................. 1897 45. Up/Down Counter ..............................1899 45.1 Overview ................................. 1900 45.2 Features ................................1901 45.3 Configuration ..............................1903 45.4 Registers ................................. 1905 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 32 I/O Map ................................1940 List of Interrupt Vector ............................. 1975 Pin Status in CPU Status ..........................1978 JTAG Boundary Scan Test ..........................1979 Revision History ................................1981 Document Revision History ............................1981 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 33 Contents CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 34: Overview
1.3 Product Line-up 1.4 Function Overview 1.5 Block Diagram 1.6 CPU 1.7 Pin Assignment 1.8 Package Dimensions 1.9 Explanation of Pin Functions 1.10 Pins of Each Function 1.11 I/O Circuit Types CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 35: Overview
1.1 Overview This section explains features of CY91590 series and basic specification. CY91590 series is Cypress 32-bit microcontroller for application control for automotives. The FR81S CPU that is compatible with the FR family is used. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 36: Features
Overview 1.2 Features This section explains features of CY91590 series. 1.2.1 FR81S CPU Core 1.2.2 Peripheral Functions CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 37: Fr81S Cpu Core
Eight protection areas can be specified commonly for instructions and the data.  Control access privilege in both privilege mode and user mode. Built-in FPU (floating point arithmetic)  IEEE754 compliant  Floating-point register 32-bit × 16 sets CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 38: Peripheral Functions
Up to 16 channels can be started simultaneously.  2 transfer factors ( Internal peripheral request and software ) A/D converter (successive approximation type)  8/10-bit resolution : 32 channels Conversion time : 3μs  CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 39 LIN synch break generation and detection; LIN synch delimiter generation  Built-in dedicated baud rate generator  An external clock can be adjusted by the reload counter  DMA transfer supported < I C > CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 40  The CR oscillation frequency can be trimmed  The main clock to sub clock(dual clock product only) ratio can be corrected by setting the real-time clock prescaler CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 41 Maximum operating frequency: 81MHz  Draw engine  Line drawing  BitBlt function  Execution from a display list  8 bpp indirect color  ARGB1555 direct color  Alpha-blending and anti-aliasing CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 42 The following interface controllers are installed. (* Each interface controller is exclusively controlled.) - Memory Controller (referred to below as MEMC) Interface: 8-bit/16-bit NOR Flash (SRAM) Capacity: 64 MB (maximum) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 43 For I/O of an external bus and GDC, 3.3V power supply used.  For the other I/O, 5V power supply used. There is a constraint about power on sequence ( 5V → 3.3V).  Under evaluation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 44: Product Line-Up
DMA Controller 16ch 1ch (64msg) 2ch (32msg) LIN-UART Multi-function serial A/D converter (8bit/10bit) 1unit/32ch Reload timer(16bit) Base timer(16bit) Free-run timer(32bit) Input capture(32bit) Output compare(32bit) PPG timer(16bit) 24ch Sound generator Real-time clock CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 45 Stop mode ( with power-shutdown ) Supported MICOM : 4.5V to 5.5V Power supply voltage GDC : 3.0V to 3.6V Operating temperature -40 to +105°C Allowable power [mW] 1250 Others Flash product On chip debugger CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 46 A/D converter (8bit/10bit) 1unit/32ch Reload timer(16bit) Base timer(16bit) Free-run timer(32bit) Input capture(32bit) Output compare(32bit) PPG timer(16bit) 24ch Sound generator Real-time clock External interrupt 16ch CR/SUB compensation function CRC generator Stepping motor control CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 47 Stop mode ( with power-shutdown ) Supported MICOM:4.5V to 5.5V Power supply voltage GDC:3.0V to 3.6V Operating temperature -40 to +105°C Allowable power [mW] 1250 Others Flash product On chip debugger CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 48 A/D converter (8bit/10bit) 1unit/32ch Reload timer(16bit) Base timer(16bit) Free-run timer(32bit) Input capture(32bit) Output compare(32bit) PPG timer(16bit) 24ch Sound generator Real-time clock External interrupt 16ch CR/SUB compensation function CRC generator Stepping motor control CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 49 Stop mode ( with power-shutdown ) Supported MICOM:4.5V to 5.5V Power supply voltage GDC:3.0V to 3.6V Operating temperature -40 to +105°C Allowable power [mW] 2500 Others Flash product On chip debugger CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 50 A/D Converter (8bit/10bit) 1unit/32ch Reload timer(16bit) Base timer(16bit) Free-run timer(32bit) Input capture(32bit) Output compare(32bit) PPG timer(16bit) 24ch Sound generator Real-time clock External interrupt 16ch CR/SUB compensation function CRC generator Stepping motor control CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 51 Stop mode ( with power-shutdown ) Supported MICOM:4.5V to 5.5V Power supply voltage GDC:3.0V to 3.6V Operating temperature -40 to +105°C Allowable power [mW] 2500 Others Flash product On chip debugger CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 52 2ch (32msg) LIN-UART Multi-function serial A/D converter (8bit/10bit) 1unit/32ch Reload timer(16bit) Base timer(16bit) Free-run timer(32bit) Input capture(32bit) 12ch Output compare(32bit) PPG timer(16bit) 24ch Sound generator Real-time clock Up/down counter Under evaluation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 53 Power supply voltage GDC:3.0V to 3.6V Operating temperature -40 to +105°C Allowable power [mW] 2500 Others Flash product On chip debugger JTAG Boundary Scan Test Yes (BGA package only supported) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 54: Function Overview
Any of four PWM/PPG/PWC/reload timer functions can be selected and used. A 32-bit timer can be used in 2 channels of cascade mode for the reload timer/PWC function. Free-run timer 32-bit up counter CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 55 Transmission interrupt factor (2 types) - No transmission operation. - Empty transmission FIFO memory (including the time of transmission) SPI(Serial Peripheral Interface) supported LIN protocol revision 2.1 supported CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 56 Internal power supply low voltage An internal power supply voltage is observed, the low voltage is set, and the detection flag is set by detection. Low-voltage detection Reset generation at low voltage detection CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 57 NMI request Non-maskable interrupt signal that is entered from NMIX pin. Debug interface Built-in OCD (On Chip Debug Unit) JTAG Boundary Scan Test BGA-320 package of CY91F59A/B is only supported. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 58: Block Diagram
Overview 1.5 Block Diagram This section shows block diagram of this series. Figure 1-1. Block Diagram: CY91F591/2/4/6/7/9 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 59 Overview Figure 1-2. Block Diagram: CY91F59A/B CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 60: Cpu
Overview 1.6 CPU This section explains general-purpose registers and dedicated registers of CPU. 1.6.1 General-purpose Registers 1.6.2 Dedicated Registers CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 61: General-Purpose Registers
 R14: FP (Frame Pointer )  R15: SP (Stack Pointer ) The initial value during reset is undefined for registers R0 to R14. Register R15 has 00000000 (SSP value). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 62: Dedicated Registers
 System stack pointer (SSP)  User stack pointer (USP)  Base pointer (BP)  FPU control register (FCR)  Exception status register (ESR)  Multiplication and division register (MD) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 63: Pin Assignment
ICU5_2 PPG9_2 P024 108 P123 OCU1 PPG8_2 P025 107 P096 INT9 P026 106 P095 PPG10_1 105 VCC5 * Pins 171 and 172 of single clock product are general purpose I/O. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 64 P024 108 P123 OCU1 PPG8_2 P025 107 P096 INT9 P026 106 P095 PPG10_1 105 VCC5 * Pins 171 and 172 of dual clock product are I/O of sub clock oscillator. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 65 P022/CS1X 110 P125/OCU3/ICU0/PPG10_2/TIN10/SCK11 P023/REX 109 P124/OCU2/ICU5_2/PPG9_2/TIN9/SOT11 P024 108 P123/OCU1/PPG8_2/TIN8/SIN11 P025 107 P096/RX0/INT9 P026/A00 106 P095/TX0/PPG10_1 105 VCC5 * Pins 171 and 172 of single clock product are general purpose I/O. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 66 110 P125/OCU3/ICU0/PPG10_2/TIN10/SCK11 P023/REX 109 P124/OCU2/ICU5_2/PPG9_2/TIN9/SOT11 P024 108 P123/OCU1/PPG8_2/TIN8/SIN11 P025 107 P096/RX0/INT9 P026/A00 106 P095/TX0/PPG10_1 105 VCC5 * Pins 171 and 172 of dual clock product are I/O of sub clock oscillator. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 67 60 129 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 110 37 59 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 38 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 68: Package Dimensions
30.00 BSC 28.00 BSC 0.50 BSC 30.00 BSC 28.00 BSC 0.45 0.60 0.75 0.30 0.50 0.70 θ 0° 8° 002-15151 ** PACKAGE OUTLINE, 208 LEAD LQFP 28.0X28.0X1.7 M M LQR208 REV** CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 69 0.20 θ 0° 4° 8° 0.12 0.20 0.17 0.22 0.27 0.45 0.60 0.75 1.00 REF 0.25 0.50 BSC 002-13651 *A PACKAGE OUTLINE, 208 LEAD TEQFP 28.0X28.0X1.7 M M LET208 REV*A CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 70 9. "+ " INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. SD / SE 0.635 10. JEDEC SPECIFICATION NO. REF: N/A. 002-16414 ** PACKAGE OUTLINE, 320 BALL FBGA 27.00X27.00X2.46 M M BYA320 REV** CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 71: Explanation Of Pin Functions
Overview 1.9 Explanation of Pin Functions The pin function list of the CY91590 series is shown. Table 1-3. List of Pin Functions: LQFP-208, TEQFP-208 I/O circuit Pin no. Pin Name Polarity Function types – Main clock oscillation input pin –...
Page 72 – P030 General-purpose I/O port (3V pin) – External bus · Address bit2 output pin – P031 General-purpose I/O port (3V pin) – External bus · Address bit3 output pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 73 External bus · Address bit22 output pin – SPI_DI SPI data input pin – P055 General-purpose I/O port (3V pin) – External bus · Address bit23 output pin – SPI_SCK SPI clock output pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 74 PWM2P2 SMC ch.2 output pin – AN18 ADC Analog 18 input pin – SIN8 Multi-function serial ch.8 serial data input pin(CY91F59A/B only) – ICU11 Input capture ch.11 input pin(CY91F59A/B only) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 75 – AN27 ADC Analog 27 input pin – ICU0_2 Input capture ch.0 input pin (2) – PPG19 PPG ch.19 output pin – UDCZIN2 Up/down counter ch.2 ZIN input pin(CY91F59A/B only) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 76 INT14 External interrupt input pin – ICU3_1 Input capture ch.3 input pin (1) – PPG8_1 PPG ch.8 output pin (1) – TIN8_1 Reload timer ch.8 event input pin (1) (CY91F59A/B only) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 77 ADC Analog 4 input pin – TOT0_1 Reload timer ch.0 output pin (1) – PPG2_1 PPG ch.2 output pin (1) – ICU8_1 Input capture ch.8 input pin (1) (CY91F59A/B only) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 78 Sound generator ch.2 SGO output pin – SIN4 LIN-UART ch.4 serial data input pin – TIN2 Reload timer ch.2 event input pin – FRCK4 Free-run timer 4 clock input pin(CY91F59A/B only) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 79 Multi-function serial ch.0 serial data input pin – INT1 INT1 External interrupt input pin – P127 General-purpose I/O port Multi-function serial ch.0 serial data output pin / I C ch.0 serial data – SOT0 I/O pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 80 – VIN4 Capture VIN4 input pin (656 mode) – General-purpose I/O port (3V pin) – RIN7 Capture R7 input pin (RGB mode) – VIN5 Capture VIN5 input pin (656 mode) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 81 Display digital G6 output pin – General-purpose I/O port (3V pin) – GOUT7 Display digital G7 output pin – General-purpose I/O port (3V pin) – BOUT2 Display digital B2 output pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 82 SMC large current port GND pin 89, 10a5, – – VCC5 +5.0v power supply pin 122, 173 1, 18, 37, – – 53, 71, VCC3 +3.3v power supply pin 175, 189 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 83 19, 36, 52, 72, 82, 88, – – GND pin 104, 123, 174, 188, *1: For the I/O circuit types see "1.11 I/O Circuit Types". *2: For switching, see "I/O Port". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 84 Test Data Out (JTAG Boundary Scan Test) AN31 ADC Analog 31 input pin P087 General-purpose I/O port – ICU4_2 Input capture ch.4 input pin (2) PPG23 PPG ch.23 output pin – PWM2M5 SMC ch.5 output pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 85 Input capture ch.0 input pin SCK11 Multi-function serial ch.11 clock I/O pin – OCU3 Output compare ch.3 output pin PPG10_2 PPG ch.10 output pin (2) TIN10 Reload timer ch.10 event input pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 86 External bus · Address bit2 output pin – P030 General-purpose I/O port (3V pin) – – GND pin – – GND pin – – GND pin – P025 General-purpose I/O port (3V pin) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 87 Capture G6 input pin (RGB mode) – General-purpose I/O port (3V pin) GIN3 Capture G3 input pin (RGB mode) – VIN7 Capture VIN7 input pin (656 mode) General-purpose I/O port (3V pin) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 88 ADC Analog 21 input pin P075 General-purpose I/O port ICU8 Input capture ch.8 input pin – SIN7_1 LIN-UART ch.7 serial data input pin PPG13_1 PPG ch.13 output pin (1) PWM1M3 SMC ch.3 output pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 89 PPG ch.9 output pin (2) TIN9 Reload timer ch.9 event input pin CAN reception data0 input pin – P096 General-purpose I/O port INT9 INT9 External interrupt input pin – – GND pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 90 External bus · Address bit1 output pin – P027 General-purpose I/O port (3V pin) – – GND pin External bus · Address bit0 output pin – P026 General-purpose I/O port (3V pin) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 91 Video switch (for External sync) output pin HSIN Capture horizontal sync signal input pin – General-purpose I/O port (3V pin) BIN7 Capture B7 input pin (RGB mode) – General-purpose I/O port (3V pin) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 92 ADC Analog 26 input pin P082 General-purpose I/O port SCK6 LIN-UART ch.6 clock I/O pin – PPG18 PPG ch.18 output pin PWM2P4 SMC ch.4 output pin UDCZIN0_1 Up/down counter ch.0 ZIN input pin (1) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 93 ADC Analog 0 input pin P100 General-purpose I/O port – SIN4_1 LIN-UART ch.4 serial data input pin (1) PPG8 PPG ch.8 output pin TIN0_1 Reload timer ch.0 event input pin (1) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 94 External bus · Address bit3 output pin – P031 General-purpose I/O port (3V pin) – – GND pin – P024 General-purpose I/O port (3V pin) – CS0X External bus · Chip select 0 output pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 95 PPG trigger 4 input pin (ch.16 to ch.19) TOT0 Reload timer ch.0 output pin SGO3 Sound generator ch.3 SGO output pin FRCK4 Free-run timer 4 clock input pin – P115 General-purpose I/O port CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 96 VCC3 +3.3v power supply pin – – VCC3 +3.3v power supply pin – – GND pin – – VCC3 +3.3v power supply pin – – VCC3 +3.3v power supply pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 97 Pin Name Polarity Function types – – GND pin – – GND pin *1: For the I/O circuit types see "1.11 I/O Circuit Types". *2: For switching, see "I/O Port". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 98: Pins Of Each Function
1.10.20 Pins of GDC (Capture 656 Mode) 1.10.21 Pins of GDC (Capture Other) 1.10.22 Pins of GDC (Display) 1.10.23 Pins of GDC (NTSC) 1.10.25 Pin of GDC (Other) 1.10.25.1. Pins of Other CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 99: Pins Of A/D Converter
ADC Analog 30 input (pin name) AN30 (pin no.) 153  ADC Analog 31 input (pin name) AN31 (pin no.) 154  A/D converter analog power supply (pin name) AVCC5 (pin no.) 111 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 100 A/D converter analog power supply (pin name) AVCC5  A/D converter upper limit reference voltage (pin name) AVRH5  A/D converter GND/ A/D converter lower limit reference voltage (pin name) AVSS5/AVRL5 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 101: Pins Of Can (Ch.0 To Ch.2)
1.9 Explanation of Pin Functions.  CAN reception data n input (pin name) RXn (n = 0 to 2)  CAN transmission data n output (pin name) TXn: (n = 0 to 2) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 102: Pins Of External Interrupt Input (Ch.0 To Ch.15)
(pin name) INT15 (pin no.)160 [CY91F59A/B] For pin number, see 1.7 Pin Assignment 1.9 Explanation of Pin Functions.  INTn External interrupt input (pin name) INTn (n = 0 to 15) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 103: Pins Of Lin-Uart (Ch.2 To Ch.7)
LIN-UART ch.7 clock I/O (pin name) SCK7_1 (pin no.)144  LIN-UART ch.7 serial data output (pin name) SOT7_1 (pin no.)143  LIN-UART ch.7 serial data input (pin name) SIN7_1 (pin no.)142 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 104 LIN-UART ch.n serial data input (pin name) SINn (n = 2 to 7)  LIN-UART ch.n serial data input (1) (pin name) SINn_1 (n = 2 to 5, and 7) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 105: Pins Of Multi-Function Serial Interface (Ch.0, Ch.1, Ch.8 To Ch.11)
C ch.n serial data I/O (pin name) SOTn (n = 0, 1, 8 to 11)  MFS ch.n serial data input (pin name) SINn (n = 0, 1, 8 to 11) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 106: Pins Of Ppg (Ch.0 To Ch.23)
PPG ch.10 output (1) (pin name) PPG10_1 (pin no.)106  PPG ch.10 output (2) (pin name) PPG10_2 (pin no.)110  PPG ch.11 output (1) (pin name) PPG11_1 (pin no.) 95 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 107 (n = 12 to 15)  PPG trigger 4 input (pin name) TRG4 (n = 16 to 19)  PPG trigger 5 input (pin name) TRG5 (n = 20 to 23) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 108: Pin Of Real Time Clock
 RTC overflow output (pin name) WOT (pin no.) 161 [CY91F59A/B] For pin number, see 1.7 Pin Assignment 1.9 Explanation of Pin Functions.  RTC overflow output (pin name) WOT CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 109: Pins Of Stepping Motor Controller (Ch.0 To Ch.5)
(pin name) PWM2P5 (pin no.) 153  SMC high current port GND (pin name) DVSS (pin no.) 125,135,145,155  SMC high current port power supply (pin name) DVCC (pin no.) 126,136,146,156 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 110 SMC ch.n output (pin name) PWM2Pn (n = 0 to 5)  SMC high current port GND (pin name) DVSS  SMC high current port power supply (pin name) DVCC CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 111: Pins Of Output Compare (Ch.0 To Ch.3)
(pin name) OCU3 (pin no.) 110 [CY91F59A/B] For pin number, see 1.7 Pin Assignment 1.9 Explanation of Pin Functions.  Output compare ch.n output (pin name) OCUn (n = 0 to 3) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 112: Pins Of Input Capture (Ch.0 To Ch.11)
(n = 0 to 11)  Input capture ch.n input (1) (pin name) ICUn_1 (n = 0 to 11)  Input capture ch.n input (2) (pin name) ICUn_2 (n = 0 to 5) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 113: Pins Of Sound Generator (Ch.0 To Ch.4)
1.9 Explanation of Pin Functions.  Sound generator ch.n SGA output (pin name) SGAn (n = 0 to 4)  Sound generator ch.n SGO output (pin name) SGOn (n = 0 to 4) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 114: Pins Of Free-Run Timer (Ch.0 To Ch.7)
(pin no.) 166 [CY91F59A/B] For pin number, see 1.7 Pin Assignment 1.9 Explanation of Pin Functions.  Free-run timer n clock input (pin name) FRCKn (n = 0 to 7) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 115: Pins Of Base Timer (Ch.0, Ch.1)
Base timer TIOAn output (pin name) TIOAn (n = 0)  Base timer TIOAn output/input (pin name) TIOAn (n = 1)  Base timer TIOBn input (pin name) TIOBn (n = 0, 1) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 116: Pins Of Reload Timer (Ch.0 To Ch.3, Ch.7 To Ch.10)
Reload timer ch.n output (1) (pin name) TOTn_1 (n = 0 to 3, 7 to 10)  Reload timer ch.n output (2) (pin name) TOTn_2 (n = 0 to 3) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 117: Pins Of Up/Down Counter (Ch.0 To Ch.2)
Up/down counter Phase B of ch.n input (pin name) UDCBINn (n = 0 to 2)  Up/down counter Phase C (reset) of ch.n input (pin name) UDCZINn (n = 0 to 2) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 118: Pins Of External Bus Interface (Gdc External Memory I/F)
(pin name) D2 (pin no.) 29  External bus/Data bit 3 I/O (pin name) D3 (pin no.) 30  External bus/Data bit 4 I/O (pin name) D4 (pin no.) 31 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 119  External bus/Chip select 0 output (pin name) CS0X  External bus/Chip select 1 output (pin name) CS1X  External bus/Data bit0 to bit15 I/O (pin name) D0 to D15 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 120: Pins Of Spi Interface (Gdc External Memory I/F)
Functions.  SPI data output (pin name) SPI_DO  SPI data input (pin name) SPI_DI  SPI clock output (pin name) SPI_SCK  SPI chip select output (pin name) SPI_XCS CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 121: Pins Of Port Function (General-Purpose I/O)
(pin name) P040 (pin no.) 63  General-purpose I/O port (3V pin) (pin name) P041 (pin no.) 64  General-purpose I/O port (3V pin) (pin name) P042 (pin no.) 65 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 122  General-purpose I/O port (pin name) P087 (pin no.) 154  General-purpose I/O port (pin name) P090 (pin no.) 157  General-purpose I/O port (pin name) P091 (pin no.) 98 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 123 (pin name) P137 (pin no.) 171  General-purpose I/O port (3V pin) (pin name) PA2 (pin no.) 176  General-purpose I/O port (3V pin) (pin name) PA3 (pin no.) 177 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 124 (pin name) PG2 (pin no.) 198  General-purpose I/O port (3V pin) (pin name) PG3 (pin no.) 199  General-purpose I/O port (3V pin) (pin name) PG4 (pin no.) 23 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 125 (pin name) PF2 to PF7  General-purpose I/O port (3V pin) (pin name) PG0 to PG7  General-purpose I/O port (3V pin) (pin name) PH3 Note: P135 is a missing number. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 126: Pins Of Gdc (Capture Rgb Mode)
(n = 2 to 7)  Capture Gn input (RGB mode) (pin name) GINn (n = 2 to 7)  Capture Bn input (RGB mode) (pin name) BINn (n = 2 to 7) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 127: Pins Of Gdc (Capture 656 Mode)
(pin no.) 183 [CY91F59A/B] For pin number, see 1.7 Pin Assignment 1.9 Explanation of Pin Functions.  Capture VINn input (656 mode) (pin name) VINn (n = 0 to 7) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 128: Pins Of Gdc (Capture Other)
1.9 Explanation of Pin Functions.  Capture vertical sync signal input (pin name) VSIN  Capture horizontal sync signal input (pin name) HSIN  Capture capture clock input (pin name) CCLK CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 129: Pins Of Gdc (Display)
Display horizontal sync signal output (Internal sync) / Display horizontal sync signal input (External sync) (pin name) HSYNC (pin no.) 25  Display reference clock input (External sync) (pin name) DCKIN (pin no.)200 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 130 (pin name) VSYNC  Display horizontal sync signal output (Internal sync) / Display horizontal sync signal input (External sync) (pin name) HSYNC  Display reference clock input (External sync) (pin name) DCKIN CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 131: Pins Of Gdc (Ntsc)
 (pin name) AVR3  NTSC signal input (pin name) VIN  For NTSC, A/D converter analog power supply (pin name) AVCC3  NTSC A/D converter GND (pin name) AVSS3 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 132: Pin Of Gdc (Hs-Spi)
(pin name) QSPI_SIOn (n = 0 to 3)  HS-SPI serial select output ch.n (pin name) QSPI_CSn (n = 0 to 3)  HS-SPI serial clock output (pin name) QSPI_CLK CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 133: Pin Of Gdc (Other)
GDC command trigger input (pin name) CMDTRG (pin no.) 200 [CY91F59A/B] For pin number, see 1.7 Pin Assignment 1.9 Explanation of Pin Functions.  GDC command trigger input (pin name) CMDTRG CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 134 (pin name) X0A  Mode pin 0 (pin name) MD0  Mode pin 1 (pin name) MD1  Mode pin 2 (pin name) MD2  Mode pin 3 (pin name) MD3 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 135 Overview  NMI interrupt input (pin name) NMIX  DEBUG I/F (pin name) DEBUGIF  External reset input (pin name) RSTX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 136: I/O Circuit Types
CMOS input Pull-down control  Schmitt input  TTL input CMOS-hys input Standby control  Automotive input CMOS input Standby control Automotive input Standby control TTL input Standby control Analog input CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 137 CMOS-hys input  Schmitt input Pull-down resistor control 50kΩ (5V cont)  CMOS-hys input  Schmitt input  Automotive input Pull-down resistor control 50kΩ (5V cont)  CMOS-hys input Automotive input CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 138 Standby control CMOS input Standby control Automotive input Standby control TTL input Standby control Analog input Input  Main oscillation I/O Standby control Input  Sub oscillation I/O Standby control CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 139 TDI/TMS/TCK (JTAG)  CMOS input Pull-up resistor control 50kΩ (1.2V Cont)  CMOS input  TRST (JTAG)  CMOS input Pull-up resistor control 50kΩ (1.2V Cont)  CMOS input Standby control CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 140 Overview Type Circuit Remarks  TDO (JTAG)  5mA output CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 141 Overview CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 142: Handling The Device
2. Handling the Device This chapter explains the notes on using this series. 2.1 Handling Precautions 2.2 Handling Device 2.3 Application Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 143: Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.
Page 144 You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions.
Page 145 Devices should be sealed in their aluminum laminate bags for storage. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 ℃/24 h...
Page 146 CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.
Page 147: Handling Device
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in the same way as for the input pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 148 When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at the free running frequency of the self oscillator circuit built in the PLL clock. This operation is not guaranteed. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 149 For the standard values, see the "Recommended Operating Conditions" of the latest data sheet. Note: For the detailed specifications of operating voltages, see the latest data sheet. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 150: Application Notes
2.3 Application Notes This section explains application notes. 2.3.1 Function Switching of a Multiplexed Port 2.3.2 Low-power Consumption Mode 2.3.3 Notes When Writing Data in a Register Having the Status Flag CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 151: Function Switching Of A Multiplexed Port
Function switching of a multiplexed port is shown. To switch between the port function and the multiplexed pin function, use the PFR (port function register). For details, see "Chapter: I/O Ports". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 152: Low-Power Consumption Mode
Take the following notes when using a monitor debugger.  Do not set a break point for the low-power consumption transition program.  Do not execute an operation step for the low-power consumption transition program. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 153: Notes When Writing Data In A Register Having The Status Flag
It is not necessary to note that the bit instruction considers this respect compared with the register to which read-modify- write (RMW) is supported. When the bit instruction is used for the register to which read-modify-write (RMW) is not supported, it is necessary to note it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 154: Cpu
This chapter explains the CPU. Overview Features CPU Operating Description Pipeline Operation Floating Point Operation Processing Data Structure Addressing Programming Model Reset and EIT Processing 3.10 Memory Protection Function (MPU) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 155: Overview
The FR81 architecture is a microcontroller architecture that uses the FR family instruction set with improved floating point functionality, memory protection functionality and on-chip debugging functionality. The integer family instruction set is compatible with the FR80. For details, see "FR Family FR81 32-bit Microcontroller Programming Manual". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 156: Features
This section explains features of the CPU. The FR family is a CPU core for 32-bit RISC-based controllers equipped with a custom Cypress architecture. In particular, this architecture is optimal as the CPU core in microcontrollers designed for embedded control applications that require high-speed control.
Page 157 Denormalized numbers are truncated to 0 or generate an exception  Floating-point register: 32-bit × 16 sets  Multiply and Add, Multiply and Sub instructions supported  Division and square root operations supported CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 158: Cpu Operating Description
CPU enters privilege mode, and changes to user mode when RETI is executed. The transition from user mode to privilege mode in the normal run state is triggered by reset or the EIT execution, and transition from privilege mode to user mode is triggered by the RETI execution. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 159 The transition from a debug state to a user state is carried by the RETI instruction. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 160: Pipeline Operation
Although the completion between each pipeline processing differs from the sequence of instruction issuances, the processing results based on the program sequence are guaranteed. For details, see "FR Family FR81 32-bit Microcontroller Programming Manual". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 161: Floating Point Operation Processing
The floating point operation processing for the CPU is shown. This series incorporates FPU. For details of the floating point operation processing, see "FR Family FR81 32-bit Microcontroller Programming Manual". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 162: Data Structure
For the integer type, little endian as the bit ordering and big endian as the byte ordering are used. For details, see "FR Family FR81 32-bit Microcontroller Programming Manual". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 163: Addressing
The CPU-based logical address is same as the physical address where memory and I/O are actually located. For details, see "FR Family FR81 32-bit Microcontroller Programming Manual". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 164: Programming Model
This section explains the programming model of the CPU. The CPU of FR81 has general-purpose registers, dedicated registers, and floating point registers. Besides these registers, the FR81 core has address-mapped system registers. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 165: General-Purpose Registers, Dedicated Registers, And Floating Point Registers
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX FR10 XXXX XXXX FR11 XXXX XXXX FR12 XXXX XXXX FR13 XXXX XXXX FR14 XXXX XXXX FR15 XXXX XXXX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 166: System Register
Read and/or write is enabled only in the privilege mode and read and/or write is disabled in the user mode. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 167: Reset And Eit Processing
This section explains Reset and EIT processing. Reset and EIT processing is the processing that is carried out by other than normal programs when Reset, Exception, Interrupt and Trap are detected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 168: Reset
In this series, the FixedVector function returns not the value written in the address of 0xF_FFFC on flash memory but the first address of + 0x0024 on flash memory to reset vector. See "Chapter 10 FixedVector Function" for details. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 169: Eit Processing
3.9.2 EIT Processing This section explains the EIT processing. The EIT processing suspends operations currently running, stores resumable information into memory and transfers control to the predetermined processing program. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 170: Vector Table
Peripheral interrupt #24 ICR24 0x35C 0x000FFF5C Peripheral interrupt #25 ICR25 0x358 0x000FFF58 Peripheral interrupt #26 ICR26 0x354 0x000FFF54 Peripheral interrupt #27 ICR27 0x350 0x000FFF50 Peripheral interrupt #28 ICR28 0x34C 0x000FFF4C CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 171 ICR46 0x304 0x000FFF04 Delay interrupt ICR47 0x300 0x000FFF00 System reserved (For REALOS use) 0x2FC 0x000FFEFC System reserved (For REALOS use) 0x2F8 0x000FFEF8 0x2F4 0x000FFEF4 For INT instruction use 0x000 0x000FFC00 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 172: Memory Protection Function (Mpu)
3.10 Memory Protection Function (MPU) This section explains the memory protection function (MPU) of the CPU. 3.10.1 Overview 3.10.2 List of Registers 3.10.3 Description of Registers 3.10.4 Operations of Memory Protection Function (MPU) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 173: Overview
The register for the memory protection function can only be accessed in a privilege mode as system registers  Data access error notification function  I/O area (00000000 to 0000FFFF ) is fixed buffer disabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 174: List Of Registers
Protection area base address register 6 0x0364 Reserved PACR6 Protection area control register 6 0x0368 PABR7 Protection area base address register 7 0x036C Reserved PACR7 Protection area control register 7 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 175: Description Of Registers
3.10.3.7 Data Access Error Status Register (DESR) 3.10.3.8 Protection Area Base Address Register 0 to 7 (PABR0 to PABR7) 3.10.3.9 Protection Area Control Register 0 to 7 (PACR0 to PACR7) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 176 This bit is for permitting data write access in privilege mode to the default areas (areas that have not been specified as protection areas). Access to default area Write access not permitted in privilege mode (Initial value) Write access permitted in privilege mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 177 When buffering is permitted, data access errors can be notified as interrupts. Buffer enable specification for the default area Buffer disabled (Initial value) Buffer enabled [bit7 to bit4] Reserved These bits are reserved. Always write "0" when writing. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 178 This bit is for enabling the memory protection function. If the memory protection function is disabled, buffering is configured as disabled for accesses to all areas. Memory protection function Memory protection function disabled (Initial value) Memory protection function enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 179 This register stores the address where an instruction access protection violation occurred when a violation has not occurred in the instruction access protection violation status register (IPVSR:IPV =0). This is not aligned. Note: This register is a prohibition of use. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 180 The access size when the violation occurred. SZ[1:0] Access size Byte Half-word Word Reserved [bit3] MD Indicates the mode of the access. Operation mode Access in user mode Access in privilege mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 181 This bit indicates that an instruction access protection violation occurred. In order to save the details of new protection violations, clear this bit. Instruction access protection violation Instruction access protection violation not detected (initial value) Instruction access protection violation detected Note: This register is a prohibition of use. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 182 This register stores the address where a data access protection violation occurred when a violation has not occurred in the data access protection violation status register (DPVSR:DPV =0). This register indicates the address requested by the CPU, and the address is not aligned. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 183 RW[1:0] Access type Read Read ( Read-modify-write ) Write Reserved [bit5, bit4] SZ[1:0] The access size when the violation occurred. SZ[1:0] Access size Byte Half word Word Reserved CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 184 Writing "0" to this bit only is valid. Writing "1" to the bit is ignored. Data access protection violation Data access protection violation not detected (initial value) Data access protection violation detected CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 185 (DESR:DAE =0). If the protection violation occurred while accessing system registers, the access address from the CPU is stored as it is without being aligned. If the result of performing a bus access is an error, the address is aligned. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 186 The access type when the error occurred. RW[1:0] Access type Read Read ( Read-modify-write ) Write Reserved [bit5, bit4] SZ[1:0] The access size when the error occurred. SZ[1:0] Access size Byte Half-word Word Reserved CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 187 The interrupt request is withdrawn by clearing this bit when the data access error interrupt is effectively done. Only "0" writing is effective to this bit. "1" writing is invalid. Data access error Data Access Error not detected (Initial value) Data Access Error detected CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 188 (PACR0 to PACR7) is the protection area. The address does not need to be aligned to the protection area size. The lower 4 bits of the PABR register are fixed at "0000 ". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 189 This bit is for enabling instruction fetch in user mode for the specified protection area. Access to the specified protection area Instruction fetch not permitted in user mode (initial value) Instruction fetch permitted in user mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 190 FFFFFFFF ASZ[4:0] Size of the specified protectorate area 00000 Reserved 00001 Reserved 00010 Reserved 00011 00100 00101 00110 128B 00111 256B 01000 512B CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 191 These bits are reserved. Always write "0" when writing. [bit0] PAE (Protection Area Enable) This bit is for enabling the memory protection function. Memory protection area Specified memory protection area disabled (Initial value) Specified memory protection area enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 192: Operations Of Memory Protection Function (Mpu)
3.10.4.1. Setting Up Memory Protection Areas 3.10.4.2. Instruction Access Protection Violation 3.10.4.3. Data Access Protection Violation 3.10.4.4. Data Access Errors 3.10.4.5. Memory Protection Operation by Delay Slot 3.10.4.6. DEAR and DESR Update 3.10.4.7. Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 193 If there are overlaps between specified protection areas, the area with the smallest number takes precedence. When the memory protection function is disabled (MPUCR:MPE =0), access is performed with access permitted to all areas and buffering disabled. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 194 The memory protection unit (MPU) monitors CPU instruction fetches and determines whether instruction fetches are permitted to the accessed areas. The instruction address when an instruction access protection violation exception occurs can be determined from the PC value saved on the system stack. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 195 If a data access protection violation occurs during the EIT processing sequence or the RETI instruction, the CPU is halted and can only be recovered by break interrupt or reset. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 196 If an illegal instruction exception (data access error) occurs during the EIT processing sequence or the RETI instruction, the CPU is halted and can only be recovered by break interrupt or reset. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 197 (instruction that cannot be arranged in the delay slot) even if there are an instruction access protection violation factor and an instruction access error factor in the lower 16-bit by arranging 32-bit instruction in the delay slot. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 198 It gives priority to the illegal instruction exception factor when the factor is generated at the same time. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 199 If the boundary of delay slot is different from that of instruction access protection area, the instruction access protection violation occurs regardless of whether the branch is established or not. PC with occurrence of exception is PC of delayed branch instruction. BEQ:D L_MYPROC2 Protection specified (instruction fetch) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 200: Operation Mode
4. Operation Mode This chapter explains the operation mode. 4.1 Overview 4.2 Features 4.3 Configuration 4.4 Register 4.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 201: Overview
This chapter explains the operation mode of this type of item decided after reset is released. See "Chapter: Power Consumption Control" for the mode of each power consumption control and the mode of each clock selection. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 202: Features
The program starts from the built-in FLASH. Serial writer mode It is a mode to which the built-in FLASH is programmed by using the serial writer. The program starts from the built-in Boot-ROM. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 203: Configuration
This section explains the configuration of the operation mode. Figure 4-1. Block Diagram Reset control circuit MD0, MD1, MD2 On-chip bus External pin address decoder P127 Mode decision External pin circuit I/O function mode selector CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 204: Register
* It depends on operation mode. [bit7 to bit0] BMOD[7:0] : Operation mode These bits indicate the current operation mode. Data writing is ineffective. BMOD[7:0] Operation mode 0101xxxx User mode 0111xx1x Serial writer mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 205: Operation
Operation Mode 4.5 Operation This section shows operations of the operation mode. 4.5.1 MD0, MD1, MD2, P127 Pins Settings 4.5.2 Fetching the Operation Mode 4.5.3 Explanation of Each Operation Mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 206: Md0, Md1, Md2, P127 Pins Settings
MD0, MD1, MD2 and P127 pins settings are shown. Table 4-1. Pin Settings Operation mode P127 User mode Serial writer mode Other combination setting is prohibited except the above-mentioned combination. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 207: Fetching The Operation Mode
The following shows an operation sequence from an occurrence of reset cause to the determination of an operation mode. Figure 4-2. Operation Mode Fetch Timing Chart When the initialization reset (INIT) occurs; Chip reset sequence "L" (Setting initialization reset) determined. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 208: Explanation Of Each Operation Mode
An external bus pin is reset immediately when a reset is entered for the external reset pin. For details, see "A.4. Pin Status in CPU Status" in "Appendix". Serial Writer Mode Contact their representatives. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 209 Operation Mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 210: Clock
5. Clock This chapter explains the clock. 5.1 Overview 5.2 Features 5.3 Configuration 5.4 Registers 5.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 211: Overview
Generation of source clocks : Selects from the clocks which are multiplied by PLL/SSCG of main clock (MCLK) or divided by 2 of main clock, or sub clock (SBCLK).  Division of source clock : Divides the source clock and generates operating clocks for supplying to each unit. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 212 Oscillation stabilization wait timer interrupt Microcontroller Clock Control GDC PLL clock (GPLLCLK) GDC PLL/SSCG * NTSC and DOTCLK Clock generation unit GDC SSCG clock (GSSCGCLK) * Excluding NTSC and DOTCLK GDC Clock Control CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 213: Features
Generates the clock for CAN prescaler. Use the PLL clock (PLLCLK) [non spread clock] when using a PLL, otherwise use the on-chip bus clock (HCLK).  For the noise decrement, the SSCG clock [spread clock] can be selected as CPU and a clock of the resource. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 214: Configuration
Figure 5-2. Connection Diagram of Clock (1)-1 Main Clock Generation Unit MTMCR: MTMCR: CSTBR: MTMCR: MTMCR: CSELR: MOSW MTIE MCEN ICR30 Main timer Interrupt Main MTMCR: MTIF Timer STOP mode Oscillation stop request CMONR: MCRDY MCLK Main clock CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 215 PLL/SSCG clock SSCG-PLL Divider Clock gear CCPSDIVR. CCSSFBR0 CCCGRCR0 SODS CCSSFBR1 CCCGRCR1 CCSSCCR0 CCCGRCR2 CCSSCCR1 PLL Enable PLLCLK PLL clock (Non-SSCG) Divider MCLK Divider Main clock PLLCR. CCPSDIVR. CCPLLFBR. IDIV PODS CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 216 1/1 to 1/8 1/1 to 1/16 clock (PCLK1) Peripheral (DIVR0.DIVB) (DIVR2.DIVP) 1/1 to 1/8 External bus clock (TCLK) (DIVR1.DIVT) Source clock (SRCCLK) Base clock PLL clock (PLLCLK) * Non spread clock CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 217 SGRCR0 SODS SDIVCR1 SGRCR1 SSSCR0 SGRCR2 SSSCR1 PLL Enable GPLLCLK GDC PLL clock Divider Clock gear ( Non - SSCG ) MCLK Main clock PEDIVCR. PGRCR0 PDIVCR PODS PGRCR1 PGRCR2 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 218 (128 to 512division) divider (Gdivider) (1 to 32division) CCPMUCR1:GDIV CCPMUCR0:FDIV Figure 5-10. Diagram of the Clock System The block diagram describes the clock system of all products lineup of CY91590. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 219: Registers
Reserved SGRCR0 SGRCR1 SGRCR2 GDC PLL_SSCG Clock Gear Setting Register 1 GDC PLL_SSCG Clock Gear Setting Register 2 Sync/Async Control Register 0x1000 SACR PICD Reserved Reserved Peripheral Interface Clock Divider CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 220: Division Configuration Register 0 : Divr0 (Division Clock Configuration Register 0)
The CPU clock (CCLK) and the on-chip bus clock (HCLK) have the same frequency as that of the base clock. DIVB[2:0] Division ratio Do not divide (Initial value) 2 division 3 division 4 division 5 division 6 division 7 division 8 division [bit4 to bit0] (Reserved) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 221: Division Configuration Register 1 : Divr1 (Division Clock Configuration Register 1)
4 division 5 division 6 division 7 division 8 division Note: Set this register so that the external bus clock (TCLK) definitely becomes 40MHz or less. [bit3 to bit0] (Reserved) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 222: Division Configuration Register 2 : Divr2 (Division Clock Configuration Register 2)
13 division 1101 14 division 1110 15 division 1111 16 division Note: Set this register to peripheral clock (PCLK1) to be sure to become 40MHz or less. [bit3 to bit0] (Reserved) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 223: Clock Source Selection Register : Cselr (Clock Source Selection Register)
CSC bit is not initialized. Initialize this bit in case of need, when the reset signal comes from RSTX terminal input or external low-voltage detection is flagged after the return from power shut-down. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 224 These bits select the source clock (SRCCLK) as follows. CKS[1:0] Source selection Division of the main clock (MCLK) by 2(Initial value) Division of the main clock (MCLK) by 2 PLL/SSCG clock (PLLSSCLK) Sub clock (SBCLK) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 225 CKS value before change Eligible values Rewritten conditions Ineligible values 00, 01 MCRDY=1 PCRDY=1 00, 01 MCRDY=1 SCRDY=1 MCRDY=1 01,11 PCRDY=1 MCRDY=1 00,10 SCRDY=1 Do not write the values which cannot be rewritten. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 226: Clock Source Monitor Register : Cmonr (Clock Source Monitor Register)
PCRDY=1 may be read immediately after changing PCEN=1 to 0. PLL enters the status of the oscillation enable regardless of the value of this bit while communicating the MDI in high-speed. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 227 These bits show the source clock (SRCCLK) currently selected. CKM[1:0] Source selection Division of main clock (MCLK) by 2 Division of main clock (MCLK) by 2 PLL/SSCG clock (PLLSSCLK) Sub clock (SBCLK) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 228: Main Timer Control Register : Mtmcr (Main Clock Timer Control Register)
If a set factor and a clear factor occur at the same time, the set factor will take precedence. The MTIF bit is not set during return from the standby mode (power shut-down) because the internal reset is generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 229 At the time of MTC=1, MTE=1 write is prohibited. When you perform a PLL/SSCG clock oscillation stabilization wait, make sure to set this bit to "0" and stop the main timer. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 230 8192.0[s] × main clock cycle 1111 × main clock cycle (Initial value) 16384.0[s] The MTS3 bit always reads "1". Change MTS[3:0] at the time when the main timer stops (MTE=0). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 231: Sub Timer Control Register : Stmcr (Sub Clock Timer Control Register)
If a set factor and a clear factor occur at the same time, the set factor will take precedence. The STIF bit is not set during return from the standby mode (power shut-down) because the internal reset is generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 232 This bit controls the operation of the sub timer as follows. Sub timer operation Operation disabled (Initial value) Operation enabled At the time of STC=1, STE=1 write is prohibited. [bit3] (Reserved) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 233 32[ms] × sub clock cycle 64[ms] × sub clock cycle 128[ms] × sub clock cycle 0.256[s] × sub clock cycle 0.512[s] × sub clock cycle 1.024[s] × (Initial value) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 234: Pll Setting Register : Pllcr (Pll Configuration Register)
(PLLSSCLK) from the main clock (MCLK). When PLL/SSCG clock oscillation is allowed (CSELR:PCEN=1), writing to this register will be disabled. [bit15, bit14] Reserved Always write "0". [bit13] (Reserved) [bit12 to bit8] Reserved Always write "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 235 The PLL/SSCG clock oscillation stabilization wait time specification in this model is 200[μs]. Reserve the 200[μs] wait time or more by either of the following methods.  Select 256[μs] POSW[3:0] or more. Reserve the 200[μs] wait time or more by software processing, regardless of POSW[3:0] settings.  CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 236 * Follow the configuration steps for your appropriate PLL/SSCG and system specifications. * See "5.5.1.3 PLL/SSCG Clock (PLLSSCLK)" for configuration samples. A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 237: Clock Stabilization Selection Register : Cstbr (Clock Stabilization Selection Register)
32[ms] × sub clock cycle 64[ms] × sub clock cycle 128[ms] × sub clock cycle 0.256[s] × sub clock cycle 0.512[s] × sub clock cycle 1.024[s] × sub clock cycle CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 238 Note that the determination detection is done while waiting for the oscillation stability when the cycle of the determination detection is shorter than a set cycle of this register when the Clock supervisor function is effective. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 239: Pll Clock Oscillation Timer Control Register : Ptmcr (Pll Clock Osc Timer Control Register)
The interrupt by the overflow of PLL/SSCG clock oscillation stabilization wait timer is controlled as follows. PTIE Operation Interrupt disabled (Initial value) Interrupt enabled (The interrupt request is output when the PTIF bit is "1".) [bit5 to bit0] (Reserved) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 240: Pll/Sscg Clock Selection Register : Ccpsselr (Cctl Pll/Sscg Clock Selection Register)
PLL or SSCG Selects PLL Selects SSCG Note: SSCG (Because it is unused) always becomes a reset status for PCSEL=0. The PLL clock is supplied to CAN and OCDU for PCSEL=1. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 241: Pll/Sscg Output Clock Division Setting Register : Ccpsdivr (Cctl Pll/Sscg Clock Division Register)
It is only dividing of the even number in the setting by this bit. The odd number dividing frequency cannot be set. Duty of the output clock becomes 50%. Please set for the PLL clock to become 128MHz or less. (The operation guarantee that exceeds 128MHz is not done. ) [bit3] (Reserved) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 242 Please set for the SSCG clock to become 128MHz or less. (The operation guarantee that exceeds 128MHz is not done. ) A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 243: Pll Feedback Division Setting Register : Ccpllfbr (Cctl Pll Fb Clock Division Register)
0001100 0001101 0001110 … …… 1100010 1100011 1100100 to Setting is prohibited 1111111 A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 244: Sscg Feedback Division Setting Register 0 : Ccssfbr0 (Cctl Sscg Fb Clock Division Register 0)
Setting is prohibited 000001 000010 000011 … …… 111101 111110 111111 Setting is prohibited A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 245: Sscg Feedback Division Setting Register 1 : Ccssfbr1 (Cctl Sscg Fb Clock Division Register 1)
Dividing frequency ratio setting 00000 00001 00010 00011 … …… 11101 11110 11111 Setting is prohibited A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 246: Sscg Configuration Setting Register 0 : Ccssccr0 (Cctl Sscg Config. Register 0)
[bit1] SMODE (Spread spectrum modulation MODE settings) : Spread spectrum modulation mode settings Sets spread spectrum modulation mode of SSCG. SMODE Modulation mode Down Spread Center Spread Down Spread Cycle to cycle jitter Target modulation rate time Period 1/Modulation frequency CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 247 SSEN Spread spectrum enable Spread spectrum disabled Spread spectrum enabled Note: Diffusivity of the spread spectrum becomes 0% regardless of a setting of the CCSSCCR1:RATESEL when SSEN is set disabled. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 248: Sscg Configuration Setting Register 1 : Ccssccr1 (Cctl Sscg Config. Register 1)
Sets the spread spectrum modulation rate of SSCG. RATESEL[2:0] Modulation rate 0.5% Setting is prohibited [bit12 to bit10] (Reserved) Writing has no effect. [bit9 to bit0] (Reserved) Always write "0" to these bits. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 249: Clock Gear Configuration Setting Register 0 : Cccgrcr0 (Cctl Clock Gear Config. Register 0)
"0" write Not affect the operation "1" write Start the operation of gear up When GRSTS=01/11 GRSTR OPeration "0" write Not affect the operation "1" write Not affect the operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 250 This bit enables the operation of clock gear. GREN Operation No use of clock gear Use of clock gear Note: This bit can be written only when PLL/SSCG clock oscillation is stopped (CSELR:PCEN = 0). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 251: Clock Gear Configuration Setting Register 1 : Cccgrcr1 (Cctl Clock Gear Config. Register 1)
These bits select the step at the start of clock gear operation and select the step between 0 and 63. GRSTN[5:0] Step number 000000 000001 000010 … …… 111101 111110 111111 Note: The gear does not operate at GRSTN =111111(number 63 of steps) setting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 252: Clock Gear Configuration Setting Register 2 : Cccgrcr2 (Cctl Clock Gear Config. Register 2)
These bits select the loop number of one step. The setting enabled number of iteration is between 1 to 256. Step is incremented/decremented when the number set to this bit is completed. GRLP[7:0] Loop number 0000_0000 0000_0001 0000_0010 … …… 1111_1101 1111_1110 1111_1111 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 253: Rtc/Pmu Clock Selection Register : Ccrtselr (Cctl Rtc Pmu Clock Selection Register)
CSC bit is not initialized. Initialize this bit in case of need, when the reset signal comes from RSTX terminal input or external low-voltage detection is flagged after the return from power shut-down. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 254: Pmu Clock Division Setting Register 0 : Ccpmucr0 (Cctl Pmu Clock Division Register 0)
Writing to this bit is ignored while the CCPMUCR0:FST bit is "1". When CCRTSELR:CSC=1 (selection of sub oscillation clock), F-division rate become undivided in spite of the value of this bit. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 255: Pmu Clock Division Setting Register 1 : Ccpmucr1 (Cctl Pmu Clock Division Register 1)
(APB) which is provided with PMU. The division rate of the PMU clock is set by this divider to meet the above relation. GDIV[4:0] Division rate Do not divide (Initial value) 00000 00001 00010 … …… 11101 11110 11111 Note: Writing to this bit is ignored while CCPMUCR1:GST bit is "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 256: Sync/Async Control Register : Sacr (Sync/Async Control Register)
[bit0] M : Synchronous/asynchronous setting register of peripheral clock(PCLK2) The peripheral clock(PCLK2) is switched when CPU selects the SSCG clock. Synchronous/asynchronous setting Synchronous (PLL/SSCG clock for CPU/peripheral) Asynchronous (PLL/SSCG clock for CPU, PLL clock for peripheral) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 257: Peripheral Interface Clock Divider : Picd (Peripheral Interface Clock Divider)
1011 12 division 1100 13 division 1101 14 division 1110 15 division 1111 16 division Note: Set this register so that the peripheral clock (PCLK2) definitely becomes 40MHz or less. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 258: Gdc Pll Control Register : Gpllcr
Always write "0" to these bits. [bit0] G_PCEN : PLL clock enabled This bit controls PLL/SSCG clock oscillation circuit for GDC as follows. G_PCEN PLL/SSCG clock enabled in GDC Oscillation stopped Oscillation enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 259: Gdc Pll Timer Setting Register : Ptimcr
× main clock period 1101 × main clock period 4096.0[s] 1110 8192.0[s] × main clock period 1111 16384.0[s] × main clock period (Initial value) "1" is always read from POSW3. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 260: Gdc Pll External Division Setting Register : Pedivcr
Setting by this bit is only division by an even number. Division by an odd number can not be set. The duty of the output clock is 50%. [bit3] (Reserved) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 261 Division by an odd number can not be set. The duty of the output clock is 50%. A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 262: Gdc Pll Multiplier Setting Register : Pdivcr
0000000-0001011 Setting is prohibited 0001100 … …… 1100010 1100011 1100100-1111111 Setting is prohibited A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 263: Gdc Pll_Sscg Multiplier Setting Register 0 : Sdivcr0
Setting is prohibited 000001 000010 000011 … …… 111101 111110 111111 Setting is prohibited A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 264: Gdc Pll_Sscg Multiplier Setting Register 1 : Sdivcr1
Multiplication rate 00000 00001 00010 00011 … …… 11101 11110 11111 Setting prohibited A set value is limited. See "5.5.1.4 Limitations when PLL/SSCG Clock is used" when you set it. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 265: Gdc Pll_Sscg Spread Spectrum Setting Register 0 : Ssscr0
These bits select spread spectrum modulation mode of SSCG in GDC from the followings: SMODE Modulation mode Down Spread Center Spread Down Spread Cycle to cycle jitter Target modulation rate time Period 1/Modulation frequency CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 266 This bit controls spread spectrum enabled /disabled of SSCG in GDC. Spread spectrum enabled Spread spectrum disabled Spread spectrum enabled Note: Diffusivity of the spread spectrum becomes 0% regardless of a setting of the SSSCR1:RATESEL when SEN is set disabled. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 267: Gdc Pll_Sscg Spread Spectrum Setting Register 1 : Ssscr1
Selects the spread spectrum modulation rate of SSCG in GDC from the followings. RATESEL[2:0] Modulation rate 0.5% Setting is prohibited [bit12 to bit10] (Reserved) Writing has no effect. [bit9 to bit0] (Reserved) Always write "0" to these bits. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 268: Gdc Pll Clock Gear Setting Register 0 : Pgrcr0
"0" write Not affect the operation "1" write Not affect the operation When PGRSTS=10 PGRSTR Operation "0" write Not affect the operation "1" write Start the operation of gear down CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 269 No use of clock gear Use of clock gear Note: This bit can be set when GPLLCR:G_PCEN=0. Only use of the clock gear up or the clock gear down is disabled. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 270: Gdc Pll Clock Gear Setting Register 1 : Pgrcr1
These bits select the step at the start of the clock gear operation. The step between 0 to 63can be selected. PGRSTN[5:0] The number of steps 000000 000001 000010 … …… 111101 111110 111111 Note: The gear does not operate at PGRSTN =111111(number 63 of steps) setting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 271: Gdc Pll Clock Gear Setting Register 2 : Pgrcr2
Selects the repeat count of 1 step. The repeat count between 1 to 256 can be set. The step is incremented/decremented when the repeat count set by this bit completes. PGRLP[7:0] The number of loop 0000_0000 0000_0001 0000_0010 … …… 1111_1101 1111_1110 1111_1111 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 272: Gdc Pll_Sscg Clock Gear Setting Register 0 : Sgrcr0
"0" write Not affect the operation "1" write Not affect the operation When SGRSTS=10 SGRSTR Operation "0" write Not affect the operation "1" write Start the operation of gear down CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 273 No use of clock gear Use of clock gear Note: This bit can be set when GPLLCR:G_PCEN=0. Only use of the clock gear up or the clock gear down is disabled. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 274: Gdc Pll_Sscg Clock Gear Setting Register 1: Sgrcr1
Selects the step at the start of the clock gear operation. The step between 0 to 63 can be selected. SGRSTN[5:0] The number of steps 000000 000001 000010 … …… 111101 111110 111111 Note: The gear does not operate at SGRSTN =111111(number 63 of steps) setting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 275: Gdc Pll _Sscg Clock Gear Setting Register 2 : Sgrcr2
These bits select the repeat count of one step. The repeat count between 1 to 256 can be set. The step is incremented/decremented when the repeat count set by this bit completes. SGRLP[7:0] The number of loops 0000_0000 0000_0001 0000_0010 … …… 1111_1101 1111_1110 1111_1111 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 276: Operation
5.5.2 Oscillation Stabilization Wait 5.5.3 Selecting the Source Clock (SRCCLK) 5.5.4 Timer 5.5.5 Notes when Clocks Conflict 5.5.6 The Clock Gear Circuit 5.5.7 Operations during MDI Communications 5.5.8 About PMU clock (PMUCLK) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 277: Oscillation Control
Clock 5.5.1 Oscillation Control This section explains oscillation control. 5.5.1.1. Main Clock (MCLK) 5.5.1.2. Sub Clock (SBCLK) 5.5.1.3. PLL/SSCG Clock (PLLSSCLK) 5.5.1.4. Limitations when PLL/SSCG Clock is used CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 278 CSTBR:MOSW[3:0] is initialized at the time of return from the reset input. Note: For the single clock products, the main clock oscillation enable is always enabled (MCEN=1). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 279 CSELR:SCEN is initialized to "0" at the time of return from the reset input or the INIT status. Notes:  For the single clock products, the sub clock oscillation enable is always disabled (SCEN=0).  For the single clock product, the sub timer cannot be used. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 280 PLLCR:POSW[3:0] goes by, supplying the clock starts. The PLL/SSCG clock oscillation stops until "1" is set to because CSELR:PCEN is initialized to "0" at the time of return from the reset input or the INIT status. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 281 SSCG macro oscillation clock frequency = (PLL/SSCG input clock frequency) × SSCG multiplication rate  PLL clock frequency = (PLL macro oscillation clock frequency) / (PEDIVCR:PODS[2:0]division ratio) SSCG clock frequency = (SSCG macro oscillation clock frequency) / (PEDIVCR:SODS[2:0] division ratio) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 282 200MHz ≤ SSCG macro oscillation clock frequency ≤ 333MHz (Down Spread)  PLL/SSCG in GDC unit: 200MHz ≤ PLL macro oscillation clock frequency ≤ 400MHz  200MHz ≤ SSCG macro oscillation clock frequency ≤ 400MHz (Down Spread)  CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 283 RATESEL 81MHz 0 / 1 000 to 110 81MHz 0 / 1 000 to 110 Spread 0% Note: Set PEDIVCR, SDIVCR0 and SDIVCR1 so as not to exceed frequency (max). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 284 Set value lower limit Set value upper limit ratio 0.50% 8 - 60 1.00% 8 - 60 2.00% 8 - 48 3.00% 8 - 31 4.00% 8 - 23 5.00% 8 - 18 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 285: Oscillation Stabilization Wait
Clock 5.5.2 Oscillation Stabilization Wait Oscillation stabilization wait is shown. This section describes oscillation stabilization wait for each clock input. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 286 The main clock does not enter the oscillation stabilization wait status when the main clock oscillates by reset of INIT and RST level because the main clock oscillation does not stop by reset of INIT and RST level. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 287 The sub clock oscillation stabilization wait time is always specified by the initial value because CSTBR:SOSW[2:0] is initialized by reset (INIT or RST). Except that case, the sub oscillation stabilization wait time can be changed by setting to CSTBR:SOSW[2:0]. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 288 Displays the clock oscillation stabilization wait status and the oscillation stabilization status  Main clock : CMONR:MCRDY ="0" , CMONR:MCRDY ="1"  PLL/SSCG clock (PLLSSCLK) : CMONR:PCRDY ="0" , CMONR:PCRDY ="1"  Sub clock (SBCLK) : CMONR:SCRDY ="0" , CMONR:SCRDY ="1" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 289: Selecting The Source Clock (Srcclk)
5.5.3 Selecting the Source Clock (SRCCLK) Selecting the source clock (SRCCLK) is shown. This section explains the selection control of the source clock (SRCCLK) which functions as the operation clock. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 290 Selecting the source clock at the time of initialization is shown. After reset (RST) the main clock (MCLK) divided by 2 is selected as the source clock(SRCCLK). After program operation the source clock can be changed by setting CSELR:CKS[1:0]. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 291 PLL/SSCG lock wait loop (loop until when PCRDY=1), or interrupt wait ↓ PLL/SSCG clock oscillation stabilization wait timer interrupt clear (PTIF=0, PTIE=0) ↓ Switches from the source clock to PLL/SSCG clock (CSELR:CKS[1:0]=00→10) ↓ CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 292 Clears sub timer interrupt (STIF=0) ↓ Switches the source clock to the sub clock (CSELR:CKS[1:0]=01→11) ↓ While selecting the sub clock as the source clock (CMONR:CKM[1:0]=11) the sub clock→the main clock divided by 2 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 293 Clears the main timer interrupt (MTIF=0) ↓ Switches the source clock to the main clock divided by 2 (CSELR:CKS[1:0]=11→01) ↓ While selecting the main clock as the source clock (CMONR:CKM[1:0]=01) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 294 When the gear is used, the gear is begun. Is the gear used? It is confirmed that the clock CCCGRCR0.GRSTS=00 has low-speed stopped. Gear Start CCCGRCR0.GRSTR=1 The gear completion is confirmed. CCCGRCR0.GRSTS=10 PLL/SSCG operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 295 When SSCG is used, peripheral resource is judged and whether it operates with PLL clock is judged. When PLL is used, it is always synchronization. Peripheral resource Asynchronously ? The relation of the CPU/peripheral clock is set synchronously. SACR.M=0 Main operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 296: Timer
5.5.4.2. Sub Clock Oscillation Stabilization Wait Timer (Sub Timer) 5.5.4.3. PLL/SSCG Clock Oscillation Stabilization Wait timer (PLL Timer) 5.5.4.4. Setting 5.5.4.5.Procedure for Setting the Timer Interrupt 5.5.4.6. Timer Operations 5.5.4.7. Watch Mode and Timer Interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 297 The main timer is operated by the main clock (MCLK). It is used for the main clock stabilization time counter. When main clock is stabilized, the timer can be used as the timer which generates interrupt after the specified period. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 298 The sub timer is operated by the sub clock (SBCLK). This timer is used for the generation of the sub clock oscillation stabilization wait time, and in the the sub clock stabilization status other than those can be used as the timer which generates interrupt after the specified period. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 299 The PLL timer is operated by the main clock and only for generation of the PLL/SSCG clock oscillation stabilization wait time. This timer can not be used for a general-purposed timer. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 300 For setting the period of the timer interrupt (MTS and STS), set the period more than PCLK1 × 5 clock. When the period of the timer interrupt is set to the extremely short time, the interrupt source may not be set. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 301 Sets the interrupt flag clear (MTMCR:MTIF=0)/(STMCR:STIF=0) ↓ Verifies the interrupt flag (MTMCR:MTIF=0)/(MTMCR:STIF=0) ↓ Program operations ↓ RETI * : Repeat reading until "0" is read because actual setting of the interrupt flag clear is delayed. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 302 MTMCR:MTS[3:0], MTMCR:MTIF is "1". While STMCR:STE=1, the sub timer counts up by the sub clock (SBCLK). If the timer overflows by the period which is selected by STMCR:STS[2:0], STMCR:STIF is "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 303 The wake-up from the watch mode is enabled by using main/sub timer interrupt or RTC interrupt. The example for switching of the watch mode in the setting of wake-up from the sub timer is shown as follows. Wake-up from the Watch Mode Figure 5-18. Wakeup CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 304: Notes When Clocks Conflict
CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 305: The Clock Gear Circuit
The clock gear circuits on PLL/SSCG of MCU and PLL/SSCG of GDC are identical hardware macro. Description can be applied to the both of them. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 306 (the end of gear up, the gear stops). After this, a clock is output at the maximum step (64 steps). After the gear stops, the clock gear start (CCCGRCR0:GRSTR,PGRCR0.PGRSTR and SGRCR0:SGRSTR) is cleared to "0" by hardware. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 307 After this, the clock of the start step set for the clock gear start step selection is output. After the gear stops, the clock gear start (CCCGRCR0:GRSTR, PGRCR0:PGRSTR and SGRCR0:SGRSTR) is cleared to "0" by hardware. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 308: Operations During Mdi Communications
) Normally, always write the same value in the register related to PLL usually. *: The register related to PLL is as follows.  CCPSDIVR:PODS  CCPLLFBR: IDIV  PLLCR:PDS CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 309: About Pmu Clock (Pmuclk)
As for the PMU clock, the main clock is selected for CCRTSELR:CSC=0 as a source clock. Please set the CCPMUCR0:FDIV register so that the frequency of the PMU clock may become 32kHz or less. The machine of F divider frequency does not influence operation for CCRTSELR:CSC=1. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 310 The frequency of the peripheral clock (PCLK1) can be calculated by the following expressions. Peripheral clock (PCLK1) frequency=(Clock frequency selecting it by CMONR:CKM) / (DIVR0:DIVB[2:0] division ratio) /(DIVR2:DVP[3:0] division ratio) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 311: Gdc Clock
"0" at PGLLCR.G_PCEN. After completing gear operation, write "0" at GPLLCR.G_PCEN. As for reset operation of GDC, see "GDC External Control " CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 312: Clock Reset State Transitions
6. Clock Reset State Transitions This chapter explains clock reset state transitions. 6.1 Overview 6.2 Device States and Transitions 6.3 Device State and Regulator Mode Corresponding to those States CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 313: Overview
For features and settings of power consumption control state, see "Chapter: Power Consumption Control". For the operations of reset, see "Chapter: Reset". For the regulator mode, see "Chapter: Regulator Control". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 314: Device States And Transitions
6.2 Device States and Transitions This section explains device states and transitions of clock reset state transitions. 6.2.1 Diagram of State Transitions 6.2.2 Explanation of Each States 6.2.3 Priority of State Transition Requests CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 315: Diagram Of State Transitions
(21) Switch from PLL to main (write instruction) (22) Illegal standby mode transition (23) Illegal standby mode transition detection reset (24) Stop mode and shutdown (write instruction) (25) Watch mode and shutdown (write instruction) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 316 The transition may be different from above diagram when connecting to OCD tool. See "Chapter: On Chip Debugger (OCD)" for details.  The sub clock mode is not transmitted to because single clock products do not include the sub clock input. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 317: Explanation Of Each States
(INIT). After the elapse of the main clock oscillation stabilization wait time (2 × main clock cycle), transits to the setting initialization (INIT) state. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 318 PLL will stop operations. Outputs a setting initialization (INIT) and a program reset (RST) to the internal circuits. Transits to the program reset (RST) state when removing the setting initialization (INIT) request and this state being released. For details, see "Chapter: Reset". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 319: Priority Of State Transition Requests
Stop mode request (register write) (generates RUN state only) ↓ Watch mode request (register write) (generates RUN state only) [ Lowest priority] Sleep mode request (register write) (generates RUN state only) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 320: Device State And Regulator Mode Corresponding To Those States
Oscillation Standby mode Main stop Stop Standby mode Main stop (Shutdown) Stop Standby mode Main Oscillation wait Oscillation Main mode PLL RUN Oscillation Main mode PLL sleep Oscillation Main mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 321 Oscillation or Stop Main mode PLL sleep Oscillation Oscillation or Stop Main mode Note: When OCD tool is connected, the regulator mode is a main mode in the above any tables. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 322: Reset
7. Reset This chapter explains the reset. 7.1 Overview 7.2 Features 7.3 Configuration 7.4 Registers 7.5 Operation Description CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 323: Overview
This section explains the overview of the reset. When a reset factor is generated, the device terminates all programs and most of the hardware operations and initializes the state. This state is referred to as a reset. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 324: Features
If there is no response within the specified time frame, a reset will be issued whether or not the bus has responded. (Reset timeout) See "Chapter : Clock Supervisor" for clock supervisor reset. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 325: Configuration
ON Block Reset control External reset Clock control External interrupt Reset mask (RTC) Reset mask (External interrupt) (*1) Power-on reset is contained (*2) Active at return from power shutdown and shutdown CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 326 Flash sec urity violation rese t factor 2bit Re se t PC LK : bit nam e of regis ter reques t fl a g Fa ctor extend counter Ge nerate rese t CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 327 When the PLL/SSCG clock is CPUAR: selected as a clock source PSTF Illegal standby mode Transition to watch mode or transition detection CPUAR: stop mode is generated reset factor PSTRE CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 328: Registers
Reserved Register 0x0590 PMUSTR Reserved Reserved Reserved PMU Status Register Note: Please note that the register of "Chapter : Power Consumption Control" is allocated in address 0x0482, 0x0591, and 0x0592. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 329: Reset Source Register : Rstrr (Reset Result Register)
RSTX pin reset detection, illegal standby mode transition detection, external low-voltage ERST detection, clock supervisor reset or simultaneous assert of RSTX and NMIX external pins Undetected Detected This bit will be cleared when it is read out. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 330 In case of a reset time out due to this reset factor, IRRST along with this bit will be "1". SRST Software reset Undetected Detected This bit will be cleared when it is read out. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 331: Reset Control Register : Rstcr (Reset Control Register)
In the RSTCR reading in the debugging state, reset is not generated. SRST Software reset No output (initial value) The set request is output by RSTCR reading. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 332: Cpu Abnormal Operation Register : Cpuar (Cpu Abnormal Operation Register)
The main oscillation determination detection is in PLL mode. No effect The set factor is given to priority when a set factor and a clear factor are generated at the same time. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 333 There is a detection flag also in RSTRR:WDG1, and the factor disappears when read once because it is read clear. Because CPUAR:HWDF is maintained, the factor is maintained until clearing. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 334: Pmu Status Register : Pmustr (Power Management Unit Status Register)
RSTX input reset No detection Detection This bit is cleared by writing "0". "1" writing is invalid. This bit is not cleared by the power-on reset. Be sure to use after clear. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 335: Operation Description
7.5 Operation Description This section explains each operation of the reset feature of this product. 7.5.1 Reset Level 7.5.2 Reset Factor 7.5.3 Reset Acceptance 7.5.4 Reset Issue 7.5.5 Reset Sequence 7.5.6 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 336: Reset Level
The following two levels of resets are available with this product. Note: Except the registers for debug interface (OCDU), the registers initialized by the reset of both levels are the same for this product. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 337 This reset level is applied at a reset by the following reset factors.  Irregular reset  Watchdog reset 0, 1 Only the following register will be initialized by this reset level.  Register of the debug interface (OCDU) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 338 CPU programs running, and the program counter will be initialized. All peripheral circuits will be initialized. When an initialize reset (INIT) is issued, a reset (RST) is issued at the same time. The reset in the entire document indicates this reset level unless otherwise specified. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 339: Reset Factor
7.5.2.5. External Low-Voltage Detection Reset 7.5.2.6. Illegal Standby Mode Transition Detection Reset 7.5.2.7. Internal Low-Voltage Detection Reset 7.5.2.8. Flash Security Violation Reset 7.5.2.9. Software Reset (RSTCR:SRST) 7.5.2.10. Recovery from Standby (Power Interception) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 340 It is a reset factor generated when detecting the power has turned on. All resets due to this reset factor are detected as an irregular reset and issue an initialize reset (INIT). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 341 Reset by this reset factor is detected as irregular reset only at the reset timeout or simultaneous assert of the NMIX pin. Other than the irregular reset detection, a reset (RST) will be issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 342 Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Whether or not an irregular reset has been detected, an initialize reset (INIT) will be issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 343 Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Whether or not an irregular reset has been detected, an initialize reset (INIT) will be issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 344 Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Other than the irregular reset detection, a reset (RST) will be issued. See "Chapter : Low Voltage Detection (External Low-Voltage Detection)" for details on voltage detection. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 345 Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Other than the irregular reset detection, a reset (RST) will be issued CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 346 The reset from this reset source is detected as irregular reset. After the detection, an initialize reset (INIT) will be issued. See "Chapter : Low Voltage Detection (Internal Low-Voltage Detection)" for details on voltage detection. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 347 Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Other than the irregular reset detection, a reset (RST) will be issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 348 #_RSTCR, R12 R0, @R12 ; Write LDUB @R12, R0 ; Read (generation of a software reset request) R0, R0 ; Dummy processing for pipeline adjustment ; Dummy processing for pipeline adjustment CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 349 (RSTRR) . The factors are displayed in the PMU status register (PMUSTR), and please confirm this register, when the microcontroller reactivates. Reset by this reset factor issues the initialization reset (INIT). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 350: Reset Acceptance
7.5.3 Reset Acceptance This section explains the acceptance processing of each reset factor. 7.5.3.1. Generation of Reset Request 7.5.3.2. Acceptance of Reset Request 7.5.3.3. Reset Issue Delay Counter 7.5.3.4. Irregular Reset CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 351 Stop the CPU programs running (same processing as sleep mode)  Acquire bus control right of the on-chip bus  Confirm that idle request has been notified to all busses CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 352 If the reset issue delay counter overflows (= reset timeout occurs), the reset request is accepted without waiting for the completion of reset request processing, and an irregular reset will be issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 353 If the delay cycle is set for a short time, it is more likely to generate an irregular reset. If the delay cycle is set for a long time, it might take a long time for a reset to be issued since the generation of a reset factor. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 354 The irregular reset does not necessarily mean that the memory contents were destroyed, but how the bus access was executed cannot be identified. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 355: Reset Issue
A reset will be issued after a reset request has been accepted. This section explains each type of reset issue. 7.5.4.1. Super Initialize Reset (SINIT) 7.5.4.2. Initialize Reset (INIT) 7.5.4.3. Reset (RST) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 356 150 to1850μs Max.80μs clock period CPU operation Oscillation Step-down circuit (PCLK× (1046+3) cycles) stabilization stabilization wait OCDU chip reset Flash step-down wait time time circuit stabilization sequence circuit wait time CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 357 Reset The following describes each reset issue sequence after reset factors of this reset have been released. Figure 7-5. Super Initialize Reset (SINIT) Sequence CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 358 None × Main clock cycle The following describes each reset issue sequence after reset factors of this reset have been released. Figure 7-6. Initialize Reset (INIT) Sequence CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 359 Because the clock settings register is initialized by reset, the period of the peripheral clock (PCLK) is 8 times the period of the main clock (MCLK). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 360: Reset Sequence
(B) during the reset period. (1) RTC (only watch mode) (2) External interrupt block (3) Power management unit (4) Clock generation block (only sub-clock selection register) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 361 20 cycles. If it requires the main clock oscillation stabilization wait time, the cycle will be extended for the time required. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 362 Once a reset cycle has completed, each reset will be released and each hardware starts running. Right after the reset release, the mode control circuit functions as a bus master of on-chip bus. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 363 The mode control circuit as a bus master will notify the operating mode, which was determined based on the mode setting value acquired, to each hardware component. Then, it will release the bus control of on-chip bus. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 364 Transition of bus control is shown. After the mode control circuit releases the bus control of on-chip bus, the CPU acquires the bus control and starts running bus operations by the CPU. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 365 After the reset release, the CPU starts fetching the reset vector (at 0x000FFFFC). After CPU acquires the bus control, the CPU accesses the reset vector through on-chip bus and retrieves the acquired reset vector to the PC to start running programs. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 366 If a forced break has occurred during the reset release, it accepts the forced break upon completion of the reset vector fetch. Thus, the PC value by the reset vector acquired will be saved at the emulator space side (stored at the E_BPCHR,E_BPCLR register). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 367: Notes
During return form standby watch mode (power shut-down) and standby stop mode (power shut-down), an internal reset is issued. Therefore any reset source without power-on reset, internal low-voltage detection reset, reset by simultaneous assert of RSTX and NMIX will not be accepted. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 368: Dma Controller (Dmac)
8. DMA Controller (DMAC) This chapter explains the DMA controller (DMAC). 8.1 Overview 8.2 Features 8.3 Configuration 8.4 Registers 8.5 Operation 8.6 DMA Usage Examples CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 369: Overview
DMAC is the module which performs the DMA (Direct Memory Access) transfer. DMA transfer controlled by this module enables the high speed transfer of variety of data without any interventions of a CPU, thus increases the system performance. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 370: Features
Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ch.4 > ch.5 > ch.6 > ch.7 > ch.8 > ch.9 > ch.10 > ch.11 > ch.12 > ch.13 > ch.14 > ch.15)  Round robin  Interrupt request : Normal completion interrupt requests, abnormal completion interrupt requests, and transfer suspend interrupt requests by transfer stop requests can be generated CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 371: Configuration
転送要 transfer 求受付求受付求受付 Determining 求受付 request priorities Transfer 転送承転送承転送承転送承 acceptance/ 認／認／認／認／ Transfer 転送終転送終 termination 転送終転送終了了 DMAC 了了 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 372: Registers
DCSR4 DTCR4 DMA transfer count register 4 0x0C48 DSAR4 DMA transfer source address register 4 0x0C4C DDAR4 DMA transfer destination address register 4 0x0C50 DCCR5 DMA channel control register 5 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 373 DSAR10 DMA transfer source address register 10 0x0CAC DDAR10 DMA transfer destination address register 10 0x0CB0 DCCR11 DMA channel control register 11 0x0CB4 DCSR11 DTCR11 DMA channel status register 11 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 374 DMA transfer destination address register 15 DMA transfer suppression NMI flag register 0x0DF4 Reserved Reserved DNMIR DILVR DMA transfer suppression interrupt level register 0x0DF8 DMACR DMA control register 0x0DFC Reserved Reserved CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 375: Dma Control Register: Dmacr (Dma Control Register)
Initial value Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Initial value Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 376 DCCRn:BLK regardless of the priority setting. Priority setting Fixed (initial value) Round robin [bit14 to bit0] Reserved Always write "0" to these bits. The read value is "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 377: Dma Channel Control Register 0 To 15: Dccr0 To 15 (Dma Channel Control Register 0 To 15)
R0,W0 R0,W0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 SAC[1:0] DAC[1:0] Initial value Attribute bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved TS[1:0] BLK[3:0] Initial value Attribute R0,W0 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 378 This bit controls the generation of interrupts when a DMA transfer is suspended by a transfer stop request from the transfer request source. As for the interrupt factor, refer to the status register (DCSRn). Transfer suspend interrupt enabled Disabled (initial value) Enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 379 (DSAR), and transfer destination address (DDAR). As for the setting, see "Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination type)". Transfer source type "Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination type)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 380 When disabling a reload, the transfer destination address register will point to the next access address to the last address at the end of the transfer. Transfer destination address reload specified Reload disabled (initial value) Reload CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 381 16-bit :halfword 32-bit :word Reserved (setting is prohibited) Set values to DSARn and DDARn registers so as not to cause a misalignment for the transfer size specified in these bits. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 382 0110 7 bytes 0111 8 bytes 1000 9 bytes 1001 10 bytes 1010 11 bytes 1011 12 bytes 1100 13 bytes 1101 14 bytes 1110 15 bytes 1111 16 bytes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 383: Dma Channel Status Register 0 To 15 : Dcsr0 To 15: (Dma Channel Status Register 0 To 15)
Transfer destination address count : DCCRn : DAC = 10  Transfer size : DCCRn: TS = 11  Demand transfer mode by software request : DCCRn:RS = 00 and DCCRn:TM = 11 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 384 Writing "1" to this bit is ignored. Make sure to clear this bit before enabling DMA operation. This bit will not be cleared automatically. Normal completion state Normal completion undetected (initial value) Normal completion CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 385: Dma Transfer Count Register 0 To 15 : Dtcr0 To 15: (Dma Transfer Count Register 0 To 15)
"0". If "0" is set for transfer count, transfer will not be performed. Also, the dedicated reload register is provided. If DCCRn:TCR is "1", the value is returned to the initial value after data transfer. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 386: Dma Transfer Source Register 0 To 15 : Dsar0 To 15: (Dma Source Address Register 0 To 15)
DSA[23:16] Initial value Attribute bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 DSA[15:8] Initial value Attribute bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DSA[7:0] Initial value Attribute CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 387 (DSAR) or the transfer destination address (DDAR) must be within the address range of peripheral under control of 16-bit peripheral bus or 32-bit peripheral bus. For details, see "Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination type)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 388: Dma Transfer Destination Register 0 To 15 : Ddar0 To 15 (Dma Destination Address Register 0 To 15)
DDA[23:16] Initial value Attribute bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 DDA[15:8] Initial value Attribute bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DDA[7:0] Initial value Attribute CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 389 (DSAR) or the transfer destination address (DDAR) must be within the address range of peripheral under control of 16-bit peripheral bus or 32-bit peripheral bus. For details, see "Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination type)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 390: Dma Transfer Suppression Nmi Flag Register : Dnmir (Dma-Halt By Nmi Register)
DMA transfer when a block unit transfer has completed. NMIHD DMA suppression control Stops the DMA transfer by the user NMI. (initial value) Does not stop the DMA transfer by the user NMI. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 391: Dma Transfer Suppression Level Register : Dilvr (Dma-Halt By Interrupt Level Register)
Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 11 is issued. 10000 Does not suppress the DMA transfer when a peripheral interrupt request is issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 392: Operation
The following explains the setting items common to all channels and the items to be set separately for each channel. Common Items for All Channels “8.5.1 DMA Operation Enable” explains the register settings for the entire DMAC control. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 393: Dma Operation Enable
Does not stop DMA transfer by the user NMI. (DNMIR:NMIHD = 1) Also, an interrupt level, which precedes the DMA transfer when an interrupt occurs, can be set by DILVR:LVL. Allowed interrupt levels are 0x1F to 0x10. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 394: Separate Items For Each Channel
1. Clear DCCRn:CE bit 2. Clear DCSRn to the initial state 3. Set DSARn 4. Set DDARn 5. Set DTCRn 6. Settings for activation by interrupt 7. Set DCCRn End settings CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 395 Request by an interrupt (DCCRn:RS = 01) Transfer Mode Setting Set the DMA transfer mode using the DCCRn:TM.  Block transfer (DCCRn:TM = 00)  Burst transfer (DCCRn:TM = 01) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 396 Using the DCCRn.DAC, set the updating of transfer destination address for DMA transfer.  Address is increased. (DCCRn:DAC = 00)  Address is decreased. (DCCRn:DAC = 01)  Address is fixed. (DCCRn:DAC = 11) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 397 Using the DCCRn:BLK, set the DMA transfer count for 1-block data transfer. The block size can be 1 to 16 times. In the 1- block transfer, data having the bit width being set by the transfer size (DCCRn:TS), is transferred for the number of times being set by the block size. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 398: Operations
These operations are repeated until the end of data transfer. During 1-block data transfer, the data having the size specified by the DCCRn:TS bit is transferred for the number of times being set by the block size. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 399 1-time transfer request causes the continuous data transfer until the end of transfer. (Data having the size set by the DCCRn:TS bit is transferred continuously for the block size × number of transfer times.) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 400 If the DCCRn:CE bit is set to "1", a transfer request is detected. When the DMA operation is enabled (DMACR:DME=1), the priority is determined and the data transfer is started immediately. When the data transfer by the transfer request has terminated, the DCCRn:CE bit is cleared automatically. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 401 Transfer request : Requests are issued for ch0, ch.1 and ch.3 simultaneously. Setting : Ch.0, ch.1 and ch.3 are set to the burst transfer mode, and data transfer occurs 3 times. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 402 Figure 8-6. Data Transfer Example 2 If Channel Priority Is Fixed Transfer request is generated on ch.1, ch.3 Transfer request is generated on ch.0 ch.0 ch.1 ch.3 ch.1 transfer end ch.3 transfer end ch.0 transfer end CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 403 (DCCRn:TS). If fixed, the address value does not change. Table 8-5 shows the address increasing or decreasing width during address updating. If an overflow occurs due to address updating, the relevant bit is discarded. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 404 8-bit ("00") Decrements by 1 Fixed ("11") Decrements ("01") 16-bit ("01") Not updated Decrements by 2 32-bit ("10") Decrements by 4 8-bit ("00") Fixed ("11") 16-bit ("01") Not updated 32-bit ("10") CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 405 (after the terminated address) regardless of the reload setting of the transfer destination address. Figure 8-9. Reloading of Transfer Destination Address Register Register settings (register write) Transfer destination Transfer destination address register address reload register Reload after the transfer Update register CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 406 If the DMACR:DME bit is cleared, all channels are stopped from operating. After a block of data has been transferred on the current channel, the data transfer is suspended. To restart data transfer, set the DMACR:DME bit.  A suspension as the DCCRn:CE bit is cleared CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 407 DCSRn:NC bit is set in the similar way as for the normal termination. Before setting the DCCRn:CE bit to "1", be sure to set the DTCRn:DTC bit to "1" or a larger value. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 408 When the DMA transfer suppressing request by DSU/OCD is asserted, a new transfer does not start and a current transfer stops with the block unit. The acknowledge is not returned to the DMA transfer suppressing from DSU/OCD. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 409 Suppresses the DMA transfer when a peripheral interrupt request having a level higher than 11 is issued. 10000 Does not suppress the DMA transfer when a peripheral interrupt request is issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 410: Dma Usage Examples
・ The progress can be checked by reading the DSAR3, DDAR3, DTCR3 registers. ・ Transfer complete can be checked by reading the DCSR3 register. Wait for DMA to finish CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 411 Check for existence of error DMA requestby interrupt Data transfer Check for existence of error Settings (DMA disa ble) Settings (com munication disa ble) Settings (clear each item) Settings (reset) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 412: Generation And Clearing Of Dma Transfer Requests
9. Generation and Clearing of DMA Transfer Requests This chapter explains the generation and clearing of DMA transfer requests. 9.1 Overview 9.2 Features 9.3 Configuration 9.4 Registers 9.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 413: Overview
DMA controller (DMAC) registers allow DMA transfer request generation factors (transfer request sources) to be set on interrupt requests from peripheral functions. The interrupt requests to be used can be selected by specifying the value corresponding to the interrupt vector number. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 414: Features
After the DMA transfer ends, the interrupt source peripheral that has issued the interrupt request to be cleared is identified if the transfer request source is a vector number to which multiple interrupt source peripherals belong. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 415: Configuration
This section explains the configuration of the generation and clearing of DMA transfer requests. Figure 9-1. Block Diagram Reverse the interrupt vector number of which DMA transfer completed. Reverse peripheral ICSEL CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 416: Registers
IO transfer request register 11 IO transfer request register 12 IO transfer request register 13 0x049C IORR12 IORR13 IORR14 IORR15 IO transfer request register 14 IO transfer request register 15 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 417: Dma Request Clear Register 0 : Icsel0 (Interrupt Clear Select Register 0)
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #16). EISEL[2:0] Clear target External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 418: Dma Request Clear Register 1 : Icsel1 (Interrupt Clear Select Register 1)
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #17). EISEL[2:0] Clear target External interrupt 8 External interrupt 9 External interrupt 10 External interrupt 11 External interrupt 12 External interrupt 13 External interrupt 14 External interrupt 15 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 419: Dma Request Clear Register 2 : Icsel2 (Interrupt Clear Select Register 2)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #18). *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B RTSEL0 Clear target Reload timer 0 Reload timer 1 Reload timer 7 Reload timer 8 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 420: Dma Request Clear Register 3 : Icsel3 (Interrupt Clear Select Register 3)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #19). *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B RTSEL1 Clear target Reload timer 2 Reload timer 3 Reload timer 9 Reload timer 10 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 421: Dma Request Clear Register 4 : Icsel4 (Interrupt Clear Select Register 4)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #38). SG_RX_SEL0 Clear target Sound generator ch.0 LIN-UART ch.7 reception completion CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 422: Dma Request Clear Register 5 : Icsel5 (Interrupt Clear Select Register 5)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #39). SG_RX_SEL1 Clear target Sound generator ch.1 LIN-UART ch.7 transmission completion CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 423: Dma Request Clear Register 6 : Icsel6 (Interrupt Clear Select Register 6)
PPG11 PPG20 PPG21 Reserved (Does not clear any interrupts) Reserved (Does not clear any interrupts) Note: Setting PPGSEL0[2:0]= "3'b110","3'b111" is prohibited. During this setting, no interrupt clear will be selected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 424: Dma Request Clear Register 7 : Icsel7 (Interrupt Clear Select Register 7)
PPG13 PPG22 PPG23 Reserved (Does not clear any interrupts) Reserved (Does not clear any interrupts) Note: Setting PPGSEL1[2:0]= "3'b110","3'b111" is prohibited. During this setting, no interrupt clear will be selected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 425: Dma Request Clear Register 8 : Icsel8 (Interrupt Clear Select Register 8)
[bit1, bit0] PPGSEL2[1:0] (PPG SELection2) : Interrupt clear selection bits for PPG4, 5, 14, 15 These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #42). PPGSEL2[1:0] Clear target PPG4 PPG5 PPG14 PPG15 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 426: Dma Request Clear Register 9 : Icsel9 (Interrupt Clear Select Register 9)
The interrupt of MFS ch.10 (status) is not covered as it is an interrupt which does not support the IIOC. Setting PPGSEL3[2:0] = "3'b101", "3'b110", "3'b111" is prohibited. During this setting, no interrupt clear will be selected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 427: Dma Request Clear Register 10 : Icsel10 (Interrupt Clear Select Register 10)
Reserved (Does not clear any interrupts) Reserved (Does not clear any interrupts) Note: Setting PPGSEL4[2:0] = "3'b101", "3'b110", "3'b111" is prohibited. During this setting, no interrupt clear will be selected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 428: Dma Request Clear Register 11 : Icsel11 (Interrupt Clear Select Register 11)
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #46). PMSTSEL[1:0] Clear target Main timer Sub timer PLL timer MFS ch.8 transmission completion CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 429: Dma Request Clear Register 12 : Icsel12 (Interrupt Clear Select Register 12)
The interrupt of Clock calibration (SUB) is not covered as it is an interrupt which does not support the IIOC. Setting SG_RX_SEL[1:0]= "2'b00", "2'b11" is prohibited. During this setting, no interrupt clear will be selected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 430: Dma Request Clear Register 13 : Icsel13 (Interrupt Clear Select Register 13)
[bit0] ICUSEL0 : Interrupt clear selection for ICU ch.0, ch.6 This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #52). ICUSEL0 Clear target ICU ch.0 ICU ch.6 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 431: Dma Request Clear Register 14 : Icsel14 (Interrupt Clear Select Register 14)
[bit0] ICUSEL1 : Interrupt clear selection for ICU ch.1, ch.7 This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #53). ICUSEL1 Clear target ICU ch.1 ICU ch.7 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 432: Dma Request Clear Register 15 : Icsel15 (Interrupt Clear Select Register 15)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #54). *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B ICUSEL2 Clear target ICU ch.2 ICU ch.8 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 433: Dma Request Clear Register 16 : Icsel16 (Interrupt Clear Select Register 16)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #55). *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B ICUSEL3 Clear target ICU ch.3 ICU ch.9 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 434: Dma Request Clear Register 17 : Icsel17 (Interrupt Clear Select Register 17)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #56). *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B ICUSEL4 Clear target ICU ch.4 ICU ch.10 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 435: Dma Request Clear Register 18 : Icsel18 (Interrupt Clear Select Register 18)
This bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #57). *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B ICUSEL5 Clear target ICU ch.5 ICU ch.11 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 436: Dma Request Clear Register 19 : Icsel19 (Interrupt Clear Select Register 19)
Setting is prohibited Reserved (Does not clear any interrupts) Reserved (Does not clear any interrupts) Note: Setting OCUSEL0[2:0]= "3'b010","3'b011","3'b100","3'b101","3'b110","3'b111" is prohibited. During this setting, no interrupt clear will be selected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 437: Dma Request Clear Register 20 : Icsel20 (Interrupt Clear Select Register 20)
Setting is prohibited Reserved (Does not clear any interrupts) Reserved (Does not clear any interrupts) Note: Setting OCUSEL1[2:0]= "3'b010","3'b011","3'b100","3'b101","3'b110","3'b111" is prohibited. During this setting, no interrupt clear will be selected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 438: Dma Request Clear Register 21 : Icsel21 (Interrupt Clear Select Register 21)
Base Timer0 IRQ1 Sound generator ch.2 MFS ch.11 reception completion Note: The interrupt of MFS ch.11 (status) is not covered as it is an interrupt which does not support the IIOC. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 439: Dma Request Clear Register 22 : Icsel22 (Interrupt Clear Select Register 22)
Sound generator ch.3 MFS ch.11 transmission completion Note: Interrupts for XBS RAM single-bit error occurrence and backup RAM single-bit error occurrence shall not be covered as they do not support the IIOC. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 440: Io Transfer Request Setting Register 0 To 15 : Iorr0 To 15 (Io Triggered Dma Request Register For Ch. 0 To 15)
DMA controller (DMAC) for the channel corresponding to these registers. IOS[5:0] Interrupt vector number (Hexadecimal) 000000 0x10 (Initial value) 000001 0x11 000010 0x12 000011 0x13 000100 0x14 000101 0x15 101100 0x3C 101101 0x3D 101110 0x3E 101111 0x3F 11xxxx Reserved CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 441 You cannot configure setting that causes interrupt requests with the same interrupt vector number to be transfer requests from multiple DMA channels (example:simultaneous setting of IORR0 = 0x42 and IORR1 = 0x42). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 442: Operation
Generation and Clearing of DMA Transfer Requests 9.5 Operation This section explains the operation of the generation and clearing of DMA transfer requests. 9.5.1 Configuration 9.5.2 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 443: Configuration
On the IORR, set the interrupt vector number of the transfer request source peripheral and the IOE bit. Set ICSEL if multiple peripherals is assigned to the vector number selected in step 1. Set the interrupt configuration-related registers for the peripheral. Configure the DMAC. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 444: Notes
DMA transfer, the interrupt will not be cleared after the completion of the requested DMA transfer.  Interrupt requests used as transfer requests are considered as interrupt requests addressed to the CPU. Therefore, configure the interrupt controller to disable interrupts. (ICR register) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 445 Generation and Clearing of DMA Transfer Requests CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 446: Fixedvector Function
10. FixedVector Function This chapter explains the FixedVector function. 10.1 Overview 10.2 Operation Explanation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 447: Overview
(0xF_FFFC) corresponding to the interrupt vector on reset. Features  Interrupt vector on reset returned by the FixedVector function  0x0007_0024 Configuration See "Figure 41-2" in "Chapter: Flash Memory" for the configuration diagram. Registers None. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 448: Operation Explanation
During reads from addresses 0x000F_FFFC to 0x000F_FFFF other than reset vector fetch (Example: the call destination when INT #00H is executed while TBR is its initial value (=0x000F_FC00)), the content of flash memory at the addresses 0x000F_FFFC to 0x000F_FFFF is returned. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 449 FixedVector Function CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 450: I/O Ports
11. I/O Ports This chapter explains the I/O ports. 11.1 Overview 11.2 Features 11.3 Configuration 11.4 Registers 11.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 451: Overview
This section explains the overview of the I/O ports. This section explains the setting for assigning to the external pins (peripherals and external bus) and using external pins as the I/O port. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 452: Features
External pins can be used for general-purpose I/O: if they are used for output, their values can be set and if they are used for input, input values assigned to them can be read. Figure 11-1. Diagram of I/O Multiplexing, I/O Relocation Multiplexing Relocation peripheral A a peripheral peripheral B peripheral C CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 453: Configuration
I/O Ports 11.3 Configuration This section explains the configuration of the I/O ports. No configuration diagram is provided. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 454: Registers
Input data direct read register 00 to 13 Input data direct read register A to H 0x0E4C PDDR12 PDDR13 Reserved Reserved 0x0E50 PDDRA PDDRB PDDRC PDDRD 0x0E54 PDDRE PDDRF PDDRG PDDRH CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 455 PPER11 Port pull-up/down enable register 00 to 13 Port pull-up/down enable register A to H 0x0ECC PPER12 PPER13 Reserved Reserved 0x0ED0 PPERA PPERB PPERC PPERD 0x0ED4 PPERE PPERF PPERG PPERH CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 456 Extended port output drive register 06 to 08 Extended port output drive register (GDC interface, graphics 0x0F3C EPODRGD EPODRGF Reserved Reserved FLASH interface) 0x0F40 PORTEN Reserved Reserved Reserved Port input enable register CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 457: Port Data Register 00 To 13, A To H : Pdr00 To Pdr13, Pdra To Pdrh (Port Data Register 00-13,A-H)
PDRH : Address 0017 (Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Reserved Initial value Attribute R1,WX R1,WX R1,WX R1,WX R,RM/W R1,WX R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 458 The pin value can be read. The PDR value can be read. PDR13[7:6] is reserved because the built-in sub clock products (dual clock products) do not have the assigned pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 459: Data Direction Register 00 To 13, A To H : Ddr00 To Ddr13, Ddra To Ddrh (Data Direction Register 00-13,A-H)
R1,WX DDRH : Address 0E17 (Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Reserved Initial value Attribute R1,WX R1,WX R1,WX R1,WX R1,WX R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 460 The assignment is as shown above. P[n] Operation Input (Initial value) Output DDR13[7:6] is reserved because the built-in sub clock products (dual clock products) do not have the assigned pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 461: Port Function Register 00 To 13, A To H : Pfr00 To Pfr13, Pfra To Pfrh (Port Function Register 00-13,A-H)
PFRA to PFRC : Address 0E30 to 0E32 (Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Initial value Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 462 (A similar process continues) The assignment is as shown above. P[n] Operation Port function or peripheral input pin (Initial value) Peripheral I/O (bidirectional) pin, peripheral output pin, or external bus pin(set by EPFR) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 463: Input Data Direct Register 00 To 13, A To H : Pddr00 To Pddr13, Pddra To Pddrh (Port Data Direct Register 00-13,A-H)
PDDRH : Address 0E57 (Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Reserved Initial value Attribute R1,WX R1,WX R1,WX R1,WX R,WX R1,WX R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 464 The assignment is as shown above. P[n] Operation Low level High level PDDR13[7:6] is reserved because the built-in sub clock products (dual clock products) do not have the assigned pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 465: Port Pull-Up/Down Control Register 00 To 13, A To H : Ppcr00 To Ppcr13, Ppcra To Ppcrh (Port Pull-Up/Down Control Register 00-13,A-H)
(Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Reserved Initial value Attribute R1, WX R1, WX R1,WX R1, WX R1, WX R1, WX R1, WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 466 See "1.9. List of Pin Functions" and "1.11. I/O Circuit Types" of "Chapter: Overview" for the presence of pull-up/pull-down. PPCR13:bit5 is a reserved bit. Writing and reading are not effective. PPCR13:P[7:6] is a reserved bit in dual clock products. Writing and reading are not effective. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 467: Port Pull-Up/Down Enable Register 00 To 13, A To H : Pper00 To Pper13, Ppera To Pperh (Port Pull-Up/Down Enable Register 00-13,A-H)
(Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Reserved Initial value Attribute R1, WX R1, WX R1,WX R1, WX R1, WX R1, WX R1, WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 468 The attribute of PPER13[5] is R/W. Write does not cause any effect. PPER13[7:6] is reserved because the built-in sub clock products (dual clock products) do not have the assigned pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 469: Port Input Level Selection Register 00 To 13, A To H : Pilr00 To Pilr13, Pilra To Pilrh (Port Input Level Register 00-13, A-H)
(Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Reserved Initial value Attribute R1, WX R1, WX R1,WX R1, WX R1, WX R1, WX R1, WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 470 TTL V =0.8[V] V =2.0[V] CMOS Schmitt V =0.3Vcc V =0.7Vcc Initial value PILR13[7:6] is reserved because the built-in sub clock products (dual clock products) do not have the assigned pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 471: Extended Port Input Level Selection Register 06 To 13 : Epilr06 To Epilr13 (Extended Port Input Level Register 06-13)
The attribute of EPILR13[5] is R/W. Write does not cause any effect. EPILR13[7:6] is reserved because the built-in sub clock products (dual clock products) do not have the assigned pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 472: Port Output Drive Register 06 To 13 : Podr06 To Podr13 (Port Output Drive Register 06-13)
The attribute of PODR13[5] is R/W. Write does not cause any effect. PODR13[7:6] is reserved because the built-in sub clock products (dual clock products) do not have the assigned pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 473 P[7:0] Initial value Attribute "11.4.9 Port Output Drive Register 06 to 13 : PODR06 to PODR13 (Port Output Drive Register 06-13)" for the setting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 474: Extended Port Output Drive Register 06 To 08 : Epodr06 To Epodr08 (Extended Port Output Drive Register 06-08)
[bit1, bit1] GDI0[1:0] GDC interface port output drive selection bits 0 These bits select following port output drive. PA[7:2], PB[7:2], PC[7:2], PD[7:2], PE[7:2], PF[7:2], PG[7:5], PG[3:0], PH[3] GDI0[1:0] Operation 2 mA 5 mA 10 mA (Initial value) 20 mA CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 475: Extended Port Output Drive Register For Graphic Digital Interface: Epodrgd
[bit3, bit2] GFI1[1:0] Graphic FLASH interface port output drive selection bits 1 These bits select following port output drive. P03[7], P04[7:0] GFI1[1:0] Operation 2 mA 5 mA 10 mA (Initial value) 20 mA CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 476: Extended Port Output Drive Register For Graphic Flash Interface: Epodrgf
[bit1, bit0] GFI0[1:0] Graphic FLASH interface port output drive selection bits 0 These bits select following port output drive. P00[7:0], P01[7:0], P02[7:0], P03[6:0], P05[7], P05[2:0] GFI0[1:0] Operation 2 mA 5 mA 10 mA (Initial value) 20 mA CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 477 Pin assignment to peripheral resources is made by the registers of PFR and EPFR. However, since all registers cannot be changed at one time, I/O relocation for outputs must be executed in the port setting state (PFRn:P[n]=0). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 478: Extended Port Function Register 00 To 58 : Epfr00 To Epfr58 (Extended Port Function Register 00-58)
Input capture ch.7 input pin selection ICU8E[1:0] Input capture ch.8 input pin selection ICU9E[1:0] Input capture ch.9 input pin selection ICU10E[1:0] Input capture ch.10 input pin selection*2 ICU11E[1:0] Input capture ch.11 input pin selection CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 479 Input from the ICUn_1pin Input from the ICUn_2 pin Reserved (Input from the ICUn_2 pin) ICUnE[1:0] Operation (n=6 to 11) Input from the ICUn pin Input from the ICUn_1pin Reserved Reserved CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 480 Attribute R1,WX R1,WX R1,WX EPFR05 : Address 0E65 (Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved TOT3E[2:0] TIN3E[1:0] Initial value Attribute R1,WX R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 481 Reload timer ch.9 TOT output pin selection TIN9E Reload timer ch.9 TIN input pin selection TOT10E[1:0] Reload timer ch.10 TOT output pin selection TIN10E Reload timer ch.10 TIN input pin selection *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 482 (n=7 to 10) No output Output from the TOTn pin Output from the TOTn_1 pin TINnE Operation (n=7 to 10) Input from the TINn pin Input from the TINn_1 pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 483 R1,WX R1,WX R1,WX EPFR09 : Address 0E69 (Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved SOT5E[1:0] SCK5E[1:0] SIN5E Initial value Attribute R1,WX R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 484 Non input/output from the SCKn Input from the SCKn / output from the SCKn Input from the SCKn_1 / output from the SCKn_1 Reserved (Input from the SCKn_1 / output from the SCKn_1) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 485 SCKnE[1:0] (n=7) Operation No input/output from the SCKn Setting is prohibited Input from the SCKn_1 / Output from the SCKn_1 Reserved (Input from the SCKn_1 / Output from the SCKn_1) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 486 I/O Ports SINnE (n=7) Operation Setting is prohibited Input from the SINn_1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 487 PPG6E[2:0] Initial value Attribute R1,WX R1,WX EPFR14 : Address 0E6E (Access: Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved PPG9E[2:0] PPG8E[2:0] Initial value Attribute R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 488 PPG ch.9 output pin selection PPG10E[2:0] PPG ch.10 output pin selection PPGnE[2:0] (n=0,2 to 10) Operation No output Output from the PPGn pin Output from the PPGn_1 pin Output from the PPGn_2 pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 489 PPG21E PPG ch.21 output pin selection PPG22E PPG ch.22 output pin selection PPG23E PPG ch.23 output pin selection PPGnE (n=16 to 23) Operation No output Output from the PPGn pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 490 PWM2MnE (n=0 to 5) Operation SMC channel n PWM M2 output disabled (Initial value) SMC channel n PWM M2 output enabled PWM2PnE, PWM1MnE and PWM1PnE (n=0 to 5) are also similar to PWM2MnE. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 491 R1,WX TXnE (n=0 to 2) : CAN channel n transmission data output enabled TXnE (n=0 to 2) Operation CAN channel n output disabled (Initial value) CAN channel n output enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 492 Reserved EPFR25D[2:0] Initial value Attribute R1,WX R1,WX R1,WX R1,WX R1,WX R/W0 R/W0 R/W0 EPFR25D[2:0] : Reserved bits "0" must be written to these bits. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 493 Setting to these bits does not affect on the operation. TIAnE (n=0, 1) Base timer TIOAn output enable TIAnE (n=0, 1) Operation Base timer TIOAn output disabled (Initial value) Base timer TIOAn output enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 494 Sound generator channel 4 SGO output enable SGA4E[1:0] Operation Sound generator channel 4 SGA output disabled (Initial value) Setting prohibited Output from the SG4_1 Setting is prohibited SGO4E[1:0] are also similar to the above. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 495 [bit1] FRCK1E : Free-run timer ch.1 clock input selection enable [bit0] FRCK0E : Free-run timer ch.0 clock input selection enable FRCKnE (n=0, 1) Operation Input from the FRCKn (Initial value) Setting is prohibited CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 496 OCUnE[1:0] (n=0 to 3) Output compare channel n output enabled OCUnE[1:0] (n=0 to 3) Operation Output compare channel n output disabled (Initial value) Output from the OCUn Setting is prohibited Setting is prohibited CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 497 Reserved SOT9E Reserved SCK9E Reserved Initial value Attribute R1,WX R1,WX R1,WX R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 Attribute R1,WX R1,WX R1,WX R0,W0 R0,W0 R0,W0 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 498 : multi-function serial interface ch.10 SCK output/input pin selection SOT11E : multi-function serial interface ch.11 SOT output/input pin selection SCK11E : multi-function serial interface ch.11 SCK output/input pin selection *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 499 C is not supported. Using ch.0 and of I C, set the register value to select _0 as relocation. I input/output of ch.8, 9, 10, and 11 is not supported. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 500 Input from UDCAIN0_1 pin Reserved Reserved BIN0E[1:0] Operation Input from UDCAIN0 pin Input from UDCBIN0_1 pin Reserved Reserved ZIN0E[1:0] Operation Input from UDCZIN0 pin Input from UDCZIN0_1 pin Reserved Reserved CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 501 Display RGB(R[n]) output disabled (Initial value) Display RGB(R[n]) output enabled GOUTnE (n=0 to 7) Display G[n] output enabled GOUTnE (n=0 to 7) Operation Display RGB(G[n]) output disabled (Initial value) Display RGB(G[n]) output enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 502 Display RGB(B[n]) output enabled Note: Lower 2-bit of ROUT/GOUT/BOUT is multiplexed with the data of external bus interface. In case of using RGB output with 8bit, D14-0 will not be available. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 503 [bit2] SPISCK : SPI Flash clock output enable SPIDO Operation SPI Flash data output disabled (Initial value) SPI Flash data output enabled SPIXCS and SPISCK are similar to the above. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 504 [bit1] EXTBUS1E : External bus output enable 1 EXTBUS1E EXTBUS0E Operation External bus output disabled regardless of PFR's setting GDC external bus output enabled (Initial value) Setting is prohibited GDC external bus output enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 505 R1,W1 EPFR20 : Address 0E74 (Access: Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved EPFR20D[6:0] Initial value Attribute R/W1 R1,W1 R1,W1 R1,W1 R1,W1 R1,W1 R1,W1 R1,W1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 506 R0,W0 R0,W0 EPFR44 : Address 0E8C (Access: Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EPFR44D[7:0] Initial value Attribute R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 507 EPFR54 : Address 0E96 (Access : Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved EPFR54D[3:0] Initial value Attribute R1,WX R1,WX R1,WX R1,WX R0,W0 R0,W0 R0,W0 R0,W0 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 508 [bit3] QUADSSELE3: HSSPI Slave select output enable 3 [bit2] QUADSSELE2: HSSPI Slave select output enable 2 [bit1] QUADSSELE1: HSSPI Slave select output enable 1 [bit0] QUADSSELE0: HSSPI Slave select output enable 0 *1: CY91F591/2/4/6//9 *2: CY91F59A/B CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 509 I/O Ports QUADSSELEn Operation Disable output Enable output n: channel number CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 510: Port Input Enable Register : Porten(Port Enable Register)
Most of pins are set input-disabled to cut off pass-through current at unstable condition. See “Appendix A.4.: Pin Status in CPU Status” for the pin that is input-disabled at initial state by reset. The input is enabled by this bit. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 511: Operation
11.5.6 Setting when Using the Base Timer TIOA1 Pin 11.5.7 Operation at Wake Up from Power Shutdown 11.5.8 Notes on switching the port function 11.5.9 Inputs interception using dedicated peripheral functions CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 512: Pin I/O Assignment
I/O direction of the pin is once set as specified by the DDR. For a pin with the A/D converter function, set the applicable bit in the analog input enable register (ADER) of the A/D converter to "Port I/O mode". For information on the setting method, see "Chapter: A/D Converter". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 513 Input I/O relocation selection circuit Input value of each pin To peripheral input value EPFR To input I/O relocation selection circuit To external bus input value To peripheral input value PDDR CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 514 Example: Since INT10 and PPG2_2 are assigned to the same pin (pin number 102-P111), external interrupt 10 can be generated at the PPG2 output by setting the pin for PPG2_2 peripheral output. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 515 Input I/O relocation selection circuit Input value of each pin To peripheral input value EPFR To input I/O relocation selection circuit To external bus input value To peripheral input value PDDR CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 516 Input I/O relocation selection circuit Input value of each pin To peripheral input value EPFR To input I/O relocation selection circuit To external bus input value To peripheral input value PDDR CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 517 Input I/O relocation selection circuit Input value of each pin To peripheral input value EPFR To input I/O relocation selection circuit To external bus input value To peripheral input value PDDR CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 518 Input I/O relocation selection circuit Input value of each pin To peripheral input value EPFR To input I/O relocation selection circuit To external bus input value PDDR To peripheral input value CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 519 Set the analog input enable register (ADER) of the A/D converter to analog input mode. See "Chapter: A/D Converter". Since the A/D converter assignment is given the highest priority, no other configuration is required. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 520: Epfr Setting Priority
If the PFR is set for the peripheral and multiple EPFR settings are overlapping for a single pin, the valid peripheral is determined based on the following priorities: Multi-function serial interface LIN-UART Sound generator Real time clock Base timer Reload timer Output compare CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 521: Notes On Input I/O Relocation Setting
When switching an input pin to another pin, if there is a difference between pin levels before and after the switch, the I/O relocation change may become a trigger input to the peripheral that uses the relevant pin as a trigger. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 522: Input Interception By Gporten
See "Appendix A.4.: Pin Status in CPU Status" for the pin that becomes an input interception. "11.4.14 Port Input Enable Register : PORTEN(PORT ENable register)"for the method of releasing the input interception. While input interception by GPORTEN, "0" will be read at applicable pins. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 523: Notes On Pins With The A/D Converter Function
A/D Converter". If analog input is enabled, inputs from ports and from peripheral functions are fixed at "0" and outputs are fixed at Hi-Z regardless of the port function register (PFR00 to PFR13, PFRA to PFRH) and extended port function register (EPFR00 to EPFR55) settings. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 524: Setting When Using The Base Timer Tioa1 Pin
I/O mode 1. If the base timer TIOA1 pin is to be used, it must be set for peripheral input for base timer I/O mode 1 (see "11.5.1.2 Peripheral Input Assignment") and set for peripheral output for all cases other than base timer I/O mode 1 (see "11.5.1.3 Peripheral Output Assignment"). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 525: Operation At Wake Up From Power Shutdown
On waking up from power shutdown, it has possibilities that the maintenance of I/O is not released. On waking up from power shutdown, PMUCTLR.IOCT bit must be written "1" for releasing the maintenance of I/O CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 526: Notes On Switching The Port Function
It is happened in the case of switching with direction change. If this output is critical for the system, please set the certain value on PDR in prior to change port function. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 527: Inputs Interception Using Dedicated Peripheral Functions
11.5.9 Inputs interception using dedicated peripheral functions The inputs interception using dedicated peripheral functions are shown below. In case of using A/D converter and SMC, "0" will be read at applicable pins for the functions. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 528: Interrupt Control (Interrupt Controller)
12. Interrupt Control (Interrupt Controller) This chapter explains the interrupt control (interrupt controller). 12.1 Overview 12.2 Features 12.3 Configuration 12.4 Registers 12.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 529: Overview
Interrupt Control (Interrupt Controller) 12.1 Overview This section explains overview the of the interrupt control (interrupt controller). The interrupt controller performs arbitration of interrupt requests. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 530: Features
Transmitting the interrupt vector number of the source with the highest priority to the CPU  Generating wakeup requests by NMI / interrupts that occur with a level other than "11111" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 531: Configuration
P e r iphe r al inter r upt *：NMI or (XBS RAM double bit error generation) or (Backup RAM double bit error generation) or (AHB RAM double bit error generation) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 532: Registers
0x0458 ICR24 ICR25 ICR26 ICR27 0x045C ICR28 ICR29 ICR30 ICR31 0x0460 ICR32 ICR33 ICR34 ICR35 0x0464 ICR36 ICR37 ICR38 ICR39 0x0468 ICR40 ICR41 ICR42 ICR43 0x046C ICR44 ICR45 ICR46 ICR47 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 533: Interrupt Control Registers 00 To 47 : Icr00 To Icr47 (Interrupt Control Register 00 To 47)
↑ 10001 (High) 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 ↓ 11110 (Low) 11111 Interrupts disabled IL4 is fixed at "1". Writing has no effect. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 534: Operation
(interrupt disable) and the interrupt factor have been generated once because it is a state with the factor of the power supply interception return. (It is executed from the reset vector. ) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 535 Interrupt Control (Interrupt Controller) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 536: External Interrupt Input
13. External Interrupt Input This chapter explains the external interrupt input. 13.1 Overview 13.2 Features 13.3 Configuration 13.4 Registers 13.5 Operation 13.6 Setting 13.7 Q&A 13.8 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 537: Overview
External Interrupt Input 13.1 Overview This section explains the overview of the external interrupt input. Interrupt request input from external interrupt input pins (INT0 to INT15). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 538: Features
This section explains features of the external interrupt input.  16 systems external interrupt input pins (INT0 to INT15)  Interrupt detection factors:4 types: ("L" level, "H" level, rising edge, falling edge) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 539: Configuration
INTx external pin EIRR To IO port controller Clear (When external interrupts are enabled, the INTx pins prevent Cleared by automatic port blocking ELVR ENIR writing zero in standby mode.) Bus access CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 540: Registers
External interrupt enable register 0 External interrupt request level register 0 External interrupt factor register 1 0x0554 EIRR1 ENIR1 ELVR1 External interrupt enable register 1 External interrupt request level register 1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 541: External Interrupt Factor Register 0/1 : Eirr0/Eirr1 (External Interrupt Request Register 0/1)
The value after resetting this register depends on the pin state after the reset.  This register will be initialized by all reset factors except recovery from standby (power shutdown) when PMUCTLR:IOCTMD=1. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 542: External Interrupt Enable Register 0/1 : Enir0/Enir1 (Enable Interrupt Request Register 0/1)
ENIR0:EN0 corresponds to INT0 pin, ENIR0:EN1 to INT1 pin, ..., ENIR0:EN7 to INT7 pin, ENIR1:EN0 to INT8 pin, ..., ENIR1:EN7 to INT15 pin.  This register will be initialized by all reset factors except recovery from standby (power shutdown) when PMUCTLR:IOCTMD=1. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 543: External Interrupt Request Level Register 0/1 : Elvr0/Elvr1 (External Interrupt Level Register 0/1)542
The factor bit in the interrupt factor register may be set by changing the interrupt request level register. Initialize the interrupt factor register after changing the interrupt request level register.  This register will be initialized by all reset factors except recovery from standby (power shutdown) when PMUCTLR:IOCTMD=1. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 544: Operation
(2) Detects interrupt signals (level/edge). (3) Generates interrupt requests. (4) Clears interrupt requests with the software. Figure 13-3. Operation of External Interrupt External interrupt Interrupt controller Resource request ELVR ICRyy EIRR ENIR ICRxx Factor CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 545 Requests to the interrupt controller will continue to be active although a request input from outside is canceled, because there is an internal factor retention circuit. To cancel requests going toward the interrupt controller, the factor register should be cleared. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 546 Factors continue to be maintained unless cleared Interrupt factors and interrupt requests to the interrupt controller when interrupts permitted H level Interrupt input Interrupt request to interrupt controller Made inactive by clearing the factor F/F CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 547: Setting
Make external pins to use for input. See "Chapter: I/O Ports". See "Chapter: I/O Ports". An input from the external pin ― External interrupt →Input signal to pins INT0 to INT15 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 548: Q&A
To enable interrupt requests Set "1". Interrupt request clear is done by the interrupt request bit (EIRR0/EIRR1:ER0 to ER7). Operation Interrupt request bit (ERn) To clear interrupt requests Write "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 549: Notes
If the reset input from RSTX pin input or the external low voltage detection flag is set after the start-up, initialize the external interrupt input register before using. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 550: Nmi Input
14. NMI Input This chapter explains the NMI input. 14.1 Overview 14.2 Features 14.3 Configuration 14.4 Register 14.5 Operation 14.6 Usage Example CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 551: Overview
This section explains the overview of the NMI input. NMI (Non Maskable Interrupt) is the non-maskable interrupt signal that is entered from the NMIX pin. The NMI can be used as a source for recovering from stop mode. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 552: Features
NMI Input 14.2 Features This section explains features of the NMI input Can be used in both stop mode (Power shut-down is included) and watch mode (Power shut-down is included). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 553: Configuration
This section explains the configuration of the NMI input. Figure 14-1. Block Diagram Falling edge NMIX detection external pin NMI interrupt NMI flag request Clear cceptance or reset Watch/Stop mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 554: Register
NMI Input 14.4 Register This section explains the register of the NMI input. This function has no register. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 555: Operation
NMIX input " L " level detected and recover from stop mode soon after entering stop mode *: The watch mode and the watch mode (power shut-down) are similarly controlled. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 556: Usage Example
This section gives an example of using the NMI function. Figure 14-3. Usage Example RSTX Master chip CY91590 NMIX UART, etc. NMI usage example ・The recovery request from sleep or standby ・Urgent communication request CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 557 NMI Input CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 558: Delay Interrupt
15. Delay Interrupt This chapter explains the delay interrupt. 15.1 Overview 15.2 Features 15.3 Configuration 15.4 Registers 15.5 Operation 15.6 Restrictions CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 559: Overview
The delay interrupt is a function for generating interrupts for the OS (operating system) to switch between tasks. This function allows interrupt requests to the CPU to be generated and cancelled by software. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 560: Features
Delay Interrupt 15.2 Features This section explains features of the delay interrupt. The delay interrupt can be generated by writing to a register. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 561: Configuration
Delay Interrupt 15.3 Configuration This section explains the configuration of the delay interrupt. Figure 15-1. Block Diagram Bus access Delay interrupt Interrupt request CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 562: Registers
[bit0] DLYI (DeLaY Interrupt enable) : Delay Interrupt Enable Bit This bit generates and clears the delay interrupt source. DLYI Description Write 0 Clears the delay interrupt source Write 1 Generates the delay interrupt source CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 563: Operation
Writing "1" to this bit generates a delay interrupt source. Writing "0" to this bit cancels the delay interrupt source. This bit functions like a standard interrupt source flag and should be cleared in the interrupt routine at the same time as when switching a task. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 564: Restrictions
Delay Interrupt 15.6 Restrictions This section explains restrictions of the delay interrupt. Do not use delay interrupts in DMA transfer requests. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 565 Delay Interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 566: Interrupt Request Batch Read
16. Interrupt Request Batch Read This chapter explains the overview, features, and configuration of the interrupt request batch read. 16.1 Overview 16.2 Features 16.3 Configuration 16.4 Registers 16.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 567: Overview
This module can read multiple interrupt requests assigned to one interrupt vector number in a batch. Interrupt requests that have been generated can be identified by using the bit search instruction of the FR80-family CPU. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 568: Features
Interrupt Request Batch Read 16.2 Features This section shows features of the interrupt request batch read. Using this module, you can easily check whether interrupts have been generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 569: Configuration
Interrupt Request Batch Read 16.3 Configuration This section shows the configuration of the interrupt request batch read. Figure 16-1. Block Diagram From Peripheral Interrupt Interrupt request controller Interrupt request batch read Bus access CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 570: Registers
IRPR13L upper-order Interrupt request batch read register 13 (#60) lower-order Interrupt request batch read register 13 (#61) upper-order 0x0434 IRPR14H IRPR14L IRPR15H Reserved Interrupt request batch read register 14 (#62) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 571 Interrupt Request Batch Read Registers Address Register function lower-order Interrupt request batch read register 14 (#62) upper-order Interrupt request batch read register 15 (#15) *1: CY91F59A/B #nn : Interrupt vector number (decimal) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 572: Interrupt Request Batch Read Register 0 Upper-Order : Irpr0H (Interrupt Request Peripheral Read Register 0H)
[bit4] RTIR8 (Reload Timer Interrupt Request 8) : Reload Timer 8 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 573: Interrupt Request Batch Read Register 0 Lower-Order : Irpr0L (Interrupt Request Peripheral Read Register 0L)
[bit4] RTIR10 (Reload Timer Interrupt Request 10) : Reload Timer 10 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 574: Interrupt Request Batch Read Register 1 Upper-Order : Irpr1H (Interrupt Request Peripheral Read Register 1H)
[bit6] ISIR0 (Multi-Function-Serial-Interface Status Interrupt Request 0): Multi-Function-Serial- Interface ch.0 Status Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 575: Interrupt Request Batch Read Register 1 Lower-Order : Irpr1L (Interrupt Request Peripheral Read Register 1L)
[bit6] ISIR1 (Multi-Function-Serial-Interface Status Interrupt Request 1) : Multi-Function-Serial-Interfacech.1 Status Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 576: Interrupt Request Batch Read Register 2 Upper-Order : Irpr2H (Interrupt Request Peripheral Read Register 2H)
[bit6] RXIR7 (RX Interrupt Request 7) : LIN-UART7 reception completion Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 577: Interrupt Request Batch Read Register 2 Lower-Order : Irpr2L (Interrupt Request Peripheral Read Register 2L)
[bit6] TXIR7 (TX Interrupt Request 7) : LIN-UART7 transmission completion Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 578: Interrupt Request Batch Read Register 3 Upper-Order : Irpr3H (Interrupt Request Peripheral Read Register 3H)
[bit3] PPGIR20 (PPG Interrupt Request 20) : PPG20 Interrupt Request [bit2] PPGIR21 (PPG Interrupt Request 21) : PPG21 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 579: Interrupt Request Batch Read Register 3 Lower-Order : Irpr3L (Interrupt Request Peripheral Read Register 3L)
[bit3] PPGIR22 (PPG Interrupt Request 22) : PPG22 Interrupt Request [bit2] PPGIR23 (PPG Interrupt Request 23) : PPG23 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 580: Interrupt Request Batch Read Register 4 Upper-Order : Irpr4H (Interrupt Request Peripheral Read Register 4H)
[bit3] UDCIR2 (Up/Down counter Interrupt Request 2) :UDC2 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 581: Interrupt Request Batch Read Register 4 Lower-Order : Irpr4L (Interrupt Request Peripheral Read Register 4L)
[bit2] ISIR10 (Multi-Function-Serial-Interface Status Interrupt Request 10) : MFS ch.10 Status Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 582: Interrupt Request Batch Read Register 5 Upper-Order : Irpr5H (Interrupt Request Peripheral Read Register 5H)
[bit3] TXIR10 (Multi-Function-Serial-Interface TX Interrupt Request 10) : MFS ch.10 Transmission Completion Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 583: Interrupt Request Batch Read Register 5 Lower-Order : Irpr5L (Interrupt Request Peripheral Read Register 5L)
[bit5] UDCIR1 (Up/Down counter Interrupt Request 1) : UDC1 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 584: Interrupt Request Batch Read Register 6 Upper-Order : Irpr6H (Interrupt Request Peripheral Read Register 6H)
See GDC manual as for description of "GDC interrupt request". As for "GDC low-voltage interrupt", see "Chapter Low Voltage Detection (Internal Low Voltage Detection)" and "Chapter Low Voltage Detection (External Low Voltage Detection)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 585: Interrupt Request Batch Read Register 6 Lower-Order : Irpr6L (Interrupt Request Peripheral Read Register 6L)
[bit4] TXIR8 (Multi-Function-Serial-Interface TX Interrupt Request 8) : MFS ch.8 Transmission Completion Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 586: Interrupt Request Batch Read Register 7 Upper-Order : Irpr7H (Interrupt Request Peripheral Read Register 7H)
[bit3] ISIR9 (Multi-Function-Serial-Interface Status Interrupt Request 9) : Multi-Function-Serial- Interface ch.9 Status Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 587: Interrupt Request Batch Read Register 7 Lower-Order : Irpr7L (Interrupt Request Peripheral Read Register 7L)
[bit4] TXIR9 (Multi-Function-Serial-Interface TX Interrupt Request 9) : MFS ch.9 Transmission Completion Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 588: Interrupt Request Batch Read Register 8 Upper-Order Irpr8H (Interrupt Request Peripheral Read Register 8H)
[bit4] FRTIR6 (FRT Interrupt Request 6) : Free-run Timer ch.6 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 589: Interrupt Request Batch Read Register 8 Lower-Order : Irpr8L (Interrupt Request Peripheral Read Register 8L)
[bit4] FRTIR7 (FRT Interrupt Request 7) : Free-run Timer ch.7 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 590: Interrupt Request Batch Read Register 9 Upper-Order : Irpr9H (Interrupt Request Peripheral Read Register 9H)
[bit6] ICUIR6 (ICU Interrupt Request 6) : Input Capture ch.6 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 591: Interrupt Request Batch Read Register 9 Lower-Order : Irpr9L (Interrupt Request Peripheral Read Register 9L)
[bit6] ICUIR7 (ICU Interrupt Request 7) : Input Capture ch.7 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 592: Interrupt Request Batch Read Register 10 Upper-Order : Irpr10H (Interrupt Request Peripheral Read Register 10H)
[bit6] ICUIR8 (ICU Interrupt Request 8) : Input Capture ch.8 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 593: Interrupt Request Batch Read Register 10 Lower-Order : Irpr10L (Interrupt Request Peripheral Read Register 10L)
[bit6] ICUIR9 (ICU Interrupt Request 9) : Input Capture ch.9 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 594: Interrupt Request Batch Read Register 11 Upper-Order : Irpr11H (Interrupt Request Peripheral Read Register 11H)
[bit6] ICUIR10 (ICU Interrupt Request 10) : Input Capture ch.10 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 595: Interrupt Request Batch Read Register 11 Lower-Order : Irpr11L (Interrupt Request Peripheral Read Register 11L)
[bit6] ICUIR11 (ICU Interrupt Request 11) : Input Capture ch.11 Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 596: Interrupt Request Batch Read Register 12 Upper-Order : Irpr12H (Interrupt Request Peripheral Read Register 12H)
[bit6] OCUIR1 (OCU Interrupt Request 1) : Output Compare ch.1 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 597: Interrupt Request Batch Read Register 12 Lower-Order : Irpr12L (Interrupt Request Peripheral Read Register 12L)
[bit6] OCUIR3 (OCU Interrupt Request 3) : Output Compare ch.3 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 598: Interrupt Request Batch Read Register 13 Upper-Order : Irpr13H (Interrupt Request Peripheral Read Register 13H)
[bit3] ISIR11 (Multi-Function-Serial-Interface Status Interrupt Request 11) : MFS ch.11 Status Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 599: Interrupt Request Batch Read Register 13 Lower-Order : Irpr13L (Interrupt Request Peripheral Read Register 13L)
[bit1] TXIR11 (Multi-Function-Serial-Interface TX Interrupt Request 11) : MFS ch.11 Transmission Completion Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 600: Interrupt Request Batch Read Register 14 Upper-Order : Irpr14H (Interrupt Request Peripheral Read Register 14H)
[bit1] DMAC6IR (DMAC 6 Interrupt Request) : DMAC ch.6 Interrupt Request [bit0] DMAC7IR (DMAC 7 Interrupt Request) : DMAC ch.7 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 601: Interrupt Request Batch Read Register 14 Lower-Order : Irpr14L (Interrupt Request Peripheral Read Register 14L)
[bit1] DMAC14IR (DMAC 14 Interrupt Request) : DMAC ch.14 Interrupt Request [bit0] DMAC15IR (DMAC 15 Interrupt Request) : DMAC ch.15 Interrupt Request Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 602: Interrupt Request Batch Read Register 15 Upper-Order : Irpr15H (Interrupt Request Peripheral Read Register 15H)
[bit4] AHB_ECC_DE : AHB RAM double bit error generation Interrupt Request *1: CY91F591/2/4/6/7/9 *2: CY91F59A/B Read value of each bit Meaning No interrupt request has been issued. An interrupt request has been issued. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 603: Operation
Note: This register does not provide a function that can be used to input external interrupts. Read registers EIRR0 and EIRR1, which are used to input external interrupts. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 604: Ppg
17. PPG This chapter explains the PPG. 17.1 Overview 17.2 Features 17.3 Configuration 17.4 Registers 17.5 Operation 17.6 Setting 17.7 Q&A 17.8 Sample Programs 17.9 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 605: Overview
(PWM) outputs. The PPG can be used in a wide range of applications because the cycle and duty of its output can be freely changed by software. Cycle value Reload Borrow Count clock Down counter Output value Match Inversion Latch Buffer Duty value CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 606: Features
Cycle = 62.5ns × (63999+1) = 4ms  Duty: Duty = Count clock × (PDUT register value + 1)  Output waveform: 6 types shown in the figure below: Figure 17-1. Output Waveforms CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 607 Borrow occurrence on the counter (match with the specified cycle) or duty match Activation triggers  Software trigger (set with software trigger bit)  Internal trigger: Trigger with register written Trigger with reload timer  External trigger CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 608: Configuration
Edge selection GCN2n:bit3 EGS1, 0 PCN : bit7, 6 Reload timer ch.0 No ef f ect on ope ration Reload timer ch.1 Rising edge External trigger (TRG) Falling edge Both edges CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 609: Registers
PPG10/PPG10_1/PPG10_2 0x0150 PPG11_1 0x0158 PPG12_1 0x0160 PPG13_1 TRG3 0x0168 PPG14_1 0x0170 PPG15_1 0x0178 PPG16 0x0180 PPG17 TRG4 0x0188 PPG18 0x0190 PPG19 0x0198 PPG20 0x01A0 PPG21 TRG5 0x01A8 PPG22 0x01B0 PPG23 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 610 PPG control status register 17 PPG timer register 18 0x0188 PTMR18 PCSR18 PPG cycle setting register 18 PPG duty setting register 18 0x018C PDUT18 PCN18 PPG control status register 18 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 611 PPG control status register 1 PPG timer register 2 0x027C PTMR2 PCSR2 PPG cycle setting register 2 PPG duty setting register 2 0x0280 PDUT2 PCN2 PPG control status register 2 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 612 PPG control status register 9 PPG timer register 10 0x02BC PTMR10 PCSR10 PPG cycle setting register 10 PPG duty setting register 10 0x02C0 PDUT10 PCN10 PPG control status register 10 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 613: Ppg Cycle Setting Register : Pcsr
Be sure to set the PPG duty setting register (PDUT) after the PPG cycle setting register is rewritten.  PPG cycle setting registers must be accessed in half-word (16-bit) or word (32-bit). (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 614: Ppg Duty Setting Register : Pdut
(The OSEL bit is the output polarity selection bit on the PPG control status register (PCN).)  PPG duty setting registers must be accessed in half-word (16-bit) or word (32-bit). (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 615: Ppg Control Status Register : Pcn
If this bit is set to "0", the PPG is enabled to perform PWM operation, thus generating a sequence of pulses.  If this bit is set to "1", the PPG generates only one pulse. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 616 Select a source edge for activation with the trigger input edge selection bits (ESG[1:0]) to the trigger input selected by the trigger specification bits (GCN10/11/12/13/14/15:TSEL3/2/1/0) of the PPG registers. [bit5] IREN : Interrupt request enable IREN Operation Interrupt request disabled Interrupt request enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 617 If the PPG output mask selection bit (PCNn:PGMS) is set to "1", setting the output polarity selection bit (OSEL) to "0" or "1" causes the output to be clamped to "L" or "H", respectively. (n = 0 to 23) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 618: General Control Register 10-13 : Gcn10 To Gcn13
GCN13 : Address 0144 (Access: Half-word) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TSEL3[3:0] TSEL2[3:0] Initial value Attribute bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TSEL1[3:0] TSEL0[3:0] Initial value Attribute CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 619 When an edge that is specified with the trigger input edge selection bits (PCNn:EGS[1:0]) (n = 0 to 15) is detected for the specified activation trigger, selected PPG0 to PPG15 will be activated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 620: General Control Register14, 15 : Gcn14, Gcn15
When an edge that is specified with the trigger input edge selection bits (PCNn:EGS[1:0]) (n = 16 to 23) is detected for the specified activation trigger, selected PPG16 to PPG23 will be activated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 621: General Control Register 20-25 : Gcn20 To Gcn25
When the state selected with the trigger input edge selection bits (EGS[1:0]) of the PPG control status register is activated by the trigger input bits (selected EN0, EN1, EN2 and EN3) with software, this trigger will activate the PPG. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 622: Ppg Timer Register : Ptmr
The count value of the 16-bit down counter can be read from these bits.  The PPG timer register (PTMRn) cannot be read correctly by the byte access. (n = 0 to 23) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 623: Ppg0 Output Division Setting Register : Ppgdiv
Setting the PPG reversed output function (PCN:OSEL = 1) is prohibited.  Setting the PPG fixed output state (PCN:PGMS, OSEL = 01, 10, 11) is prohibited.  Setting is prohibited when PCSR = PDUT. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 624: Operation
This section explains the operation of the PPG. There are 24 of PPG (Programmable Pulse Generator) to output programmable pulses independently/systematically. Followings are explanations for each operation mode. 17.5.1 PWM Operation 17.5.2 One-shot Operation 17.5.3 Restart Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 625: Pwm Operation
17.5.1 PWM Operation This section explains the PWM operation of the PPG. During the PWM operation, programmable variable-duty pulses are output at the PPG pin. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 626 Cycle = {Cycle value (PCSR) + 1} × Count clock Duty = {Duty value (PDUT) + 1} × Count clock Time to pulse output = [Cycle value (PCSR) - duty value (PDUT)] × Count clock CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 627: One-Shot Operation
17.5.2 One-shot Operation This section explains the one-shot operation of the PPG. During the one-shot operation, one-shot pulses are output at the PPG pin. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 628 (8) Output level inversion at the PPG pin (9) Counter decrement (10) Counter borrow occurrence (11) Clearing PPG pin output level (restoration to normal state) (12) End of operation sequence (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 629: Restart Operation
When restart operation is disabled, second and latter triggers will be invalid for both the PWM operation and the one-shot operation. (Triggers after the down counter is stopped will still be valid even if second and latter triggers occur.) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 630: Setting
Trigger generation  External trigger 17.4.3  Software trigger PPG control status (PCN0 to PCN23)  Reload timer See "CHAPTER: RELOAD TIMER".  GCN20/21/22/23/24/25:EN bit General control 20/21/22/23/24/25 17.4.6 (GCN20/21/22/23/24/25) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 631 17.7.12 Controller)". PPG interrupt factor selection 17.7.13 (Activation trigger generation, borrow generation, duty match) PPG control status (PCN0 to PCN23) PPG interrupt setting Interrupt request clear 17.7.14 Interrupt request enable CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 632: Q&A
17.7.9 How to Change a Pin to a PPG Output Pin 17.7.10 How to Generate Activation Trigger 17.7.11 How to Stop PPG Operation 17.7.12 Interrupt-related Registers 17.7.13 Type and Selection of Interrupts 17.7.14 How to Enable/Disable/Clear Interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 633: How To Set (Rewrite) Cycle And Duty Values
PCSR register value = PDUT register value to FFFF (65535) PDUT register value = 0 to PCSR register value Note: Be sure to set the duty value after the cycle is set.(See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 634: How To Enable/Stop Ppg Operation
PPG operation enable bit (CNTE) How to stop PPG operation Set to "0" How to enable PPG operation Set to "1" Activate the PPG after the PPG operation is enabled. (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 635: How To Set Ppg Operation Mode (Pwm/One-Shot)
Use the mode selection bit (PCNn:MDSE) for selecting an operation mode. (n=0 to 23) Operating mode Mode selection bit (MDSE) How to set to PWM operation Set to "0" How to set to one-shot operation Set to "1" (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 636: How To Restart
This section explains how to restart the PPG. Restart enable PPG restart can be enabled while the PPG is running. Use the restart enable bit (PCNn:RTRG) for setting.(n = 0 to 23) (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 637: Type And Selection Of Count Clock
16MHz 125.0 ns to 4.096 ms PCLK/4 4MHz 500 ns to 16.384 ms 2.0 μs to 65.536 ms PCLK/16 1MHz 8.0 μs to 262.144 ms PCLK/64 250kHz (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 638: How To Fix The Ppg Pin Output Level
Write the same value as the cycle setting register value to the duty cycle setting register setting register on occurrence of an interrupt caused by a compare match. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 639: Type And Selection Of Activation Trigger
How to select EN3 bit of the GCN20 register Set to "0011" How to select reload timer 0 Set to "0100" How to select reload timer 1 Set to "0101" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 640 Trigger is generated at "L" → "H" (rising) Set to "01" Trigger is generated at "H" → "L" (falling) Set to "10" Trigger is generated at both edges Set to "11" (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 641: How To Reverse The Output Polarity
Use the PPG output polarity selection bit (PCNn:OSEL) for setting. (n = 0 to 23) ("Normal state" is a state which does not output pulses.) Output level in the normal state PPG output polarity selection bit (OSEL) Set to "0" Set to "1" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 642: How To Change A Pin To A Ppg Output Pin
17.7.9 How to Change a Pin to a PPG Output Pin The section explains how to change a pin to a PPG output pin. Set the pins as peripheral output. For setting, see "Chapter: I/O Ports". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 643: How To Generate Activation Trigger
The PPG will not be activated on the activation trigger before the PPG operation is enabled. Be sure to enable the PPG operation before generating the activation trigger. (See "17.7.2 How to Enable/Stop PPG Operation?".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 644: How To Stop Ppg Operation
17.7.11 How to Stop PPG Operation This section explains how to stop the PPG operation. Set the PPG stop bit. (See "17.7.2 How to Enable/Stop PPG Operation?".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 645: Interrupt-Related Registers
Clear the interrupt request flags (PCNn:IRQF) by software before the recovery from the interrupt process as the flags will not be cleared automatically. (Write "0" to the IRQF bit) (n = 0 to 23) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 646: Type And Selection Of Interrupts
Down counter borrow (match with the specified cycle) Set to "01" Duty match Set to "10" Down counter borrow (match with the specified cycle) or duty match Set to "11" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 647: How To Enable/Disable/Clear Interrupt
Use the interrupt request bit (PCNn:IRQF) for clearing interrupt requests. (n = 0 to 23) Operation Interrupt request bit (IRQF) How to clear interrupt request Write "0" (See "17.9 Notes".) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 648: Sample Programs
/* bit14 = 1 STRG Software trigger */ <Others> (Note) You need settings for clock and “_set_il”(numerical value) in advance. See “Chapter: Clock” and “Chapter: Interrupt Control (Interrupt Controller)” for details. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 649 IO_TMCSR0 = IO_TMCSR0 | 0x0001; /* bit0 = 1 TRG software trigger */ (Note) You need settings for clock and “_set_il”(numerical value) in advance. See “Chapter: Clock” and “Chapter :Interrupt Control (Interrupt Controller)” for details. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 650 IO_GCN20 = 0x02; /* bit1 = 1 EN1 bit of GNC20 */ Trigger level = "H" GCN20.EN1 <Others> (Note) You need settings for clock and “_set_il”(numerical value) in advance. See “Chapter: Clock” and “Chapter: Interrupt Control (Interrupt Controller)” for details. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 651 #pragma intvect PPG4_int 42 <Interrupt vector> Vector table setting <Others> (Note) You need settings for clock and “_set_il”(numerical value) in advance. See “Chapter: Clock” and “Chapter: Interrupt Control (Interrupt Controller)” for details. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 652: Notes
Be sure to write the values (1) PCSRn and (2) PDUTn in that order when writing a cycle value (PCSR) and a duty value (PDUT). Notes on writing cycle values (PCSR) and duty values (PDUT) are shown below: CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 653 The interrupt request flag will be set to "1" because of borrow occurrence on the counter.  The interrupt request flag will be set to "1" because of such interrupt factors as software trigger, external trigger, or GATE signal trigger. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 654: Watchdog Timer
18. Watchdog Timer This chapter explains the watchdog timer. 18.1 Overview 18.2 Features 18.3 Configuration 18.4 Registers 18.5 Operation 18.6 Usage Example CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 655: Overview
This series has two watchdog timers that can detect software and hardware running out of control, and generate reset requests. Figure 18-1. Block Diagram (Overview) Bus Access Watchdog 0 Peripheral clock (Software Watchdog) Watchdog reset 0 (PCLK) Watchdog 1 Watchdog reset 1 (Hardware Watchdog) oscillator CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 656: Features
Count stop conditions The count stops when using ICE, during sleep mode, watch mode, stop mode, and when waiting for the oscillator to stabilize when recovering from standby mode. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 657: Configuration
CR oscillator Watchdog reset 1 CR oscillator WDT1 stops in sleep mode and standby mode overflow Overflow Overflow cycle period selection selection CR oscillator Watchdog timer 1 (24-bit up counter) WDTCR1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 658: Registers
Table 18-1. Registers map Registers Address Register function Watchdog control register 0 Watchdog timer 0 clear register 0x003C WDTCR0 WDTCPR0 WDTCR1 WDTCPR1 Watchdog timer 1 cycle information register Watchdog timer 1 clear register CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 659: Watchdog Control Register 0 : Wdtcr0 (Watchdog Timer Configuration Register 0)
Generates a reset when detected Writing to this bit is ignored after watchdog timer 0 activates. [bit5, bit4] Reserved "0" is always written to these bits. The reading value is "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 660 Writing to these bits are ignored after watchdog timer 0 activates. Watchdog timer 0 is not counted during periods where the CPU is not operating. Counting is performed while the CPU is operating even if DMA transfers are being performed. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 661: Watchdog Timer 0 Clear Register : Wdtcpr0 (Watchdog Timer Clear Pattern Register 0)
0 is issued at that time. The value read out from this register is always "0x00" regardless of the value written. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 662: Watchdog Timer 1 Cycle Information Register : Wdtcr1 (Watchdog Timer Cycle Information Register 1)
These bits configure the number of cycles from when watchdog timer 1 was last cleared until watchdog reset 1 is issued. The cycle is fixed to 2 cycles. Writing to these bits are ignored. WT[3:0] Watchdog timer 1 cycle 0110 CR oscillator × 2 cycles (initial value, fixed) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 663: Watchdog Timer 1 Clear Register : Wdtcpr1 (Watchdog Timer Clear Pattern Register 1)
When a value other than "0xA5" is written, the watchdog reset 1 is issued at that time. The value read out from this register is always "0x00" regardless of the value written. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 664: Operation
Because the peripheral clock is stopped during the oscillation stabilization wait time of the source clock, the watchdog timer count also stops. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 665 Watchdog timer 1 generates a watchdog reset request under the following conditions.  An overflow of the watchdog timer cycle occurs  A value other than "0xA5" is written to WDTCPR1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 666: Usage Example
• Clear watchdog 1. Within pe riodic • Perform other processing as necessary. (Various calibrations, etc.) • Perform other processing as necessary. (Various calibrations, etc.) interrupt se rvice by timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 667 Watchdog Timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 668: Base Timer
19. Base Timer This chapter explains the base timer. 19.1 Overview 19.2 Features 19.3 Configuration 19.4 Registers 19.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 669: Overview
This series includes the base timer for 2 channels. These base timers provide the following functions:  16/32-bit reload timer  16-bit PWM timer  16-bit PPG timer  16/32-bit PWC timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 670: Features
This series includes the base timer for 2 channels. Each channel selects and uses appropriate ones of the following functions: 19.2.1 16/32-bit Reload Timer 19.2.2 16-bit PWM Timer 19.2.3 16/32-bit PWC Timer 19.2.4 16-bit PPG Timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 671: 16/32-Bit Reload Timer
Interrupt request An interrupt request can be generated in one of the following events:  IRQ0: When an underflow occurs  IRQ1: When a 16/32-bit reload timer activation trigger is detected CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 672: 16-Bit Pwm Timer
An interrupt request can be generated in one of the following events:  IRQ0: When an underflow occurs or counting is performed up to a preset value (duty)  IRQ1: When a 16-bit PWM timer activation trigger is detected CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 673: 16/32-Bit Pwc Timer
The 16/32-bit PWC timer can be reactivated when an activation trigger is detected during counting. Interrupt request An interrupt request can be generated in one of the following events:  IRQ0: When an overflow occurs  IRQ1: When measurement ends CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 674: 16-Bit Ppg Timer
IRQ0: When an underflow occurs based on the value of the base timer x H width setting reload register (BTxPRLH).  IRQ1: When a 16-bit PPG timer activation trigger is detected. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 675: Configuration
Trigger logic Interrupt logic Trigger logic Interrupt logic I/O selection logic Base Timer TIOA0 TIOA1 TIOB0 TIOB1 (Input for I/O mode1and output or unused for other than I/O mode 1) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 676: Registers
Table 19-1. Table of Base Addresses (Base_addr) and External Pins Channel number Base address External pin 0x0080 TIOA0, TIOA1, TIOB0, and TIOB1 are assigned based on the BTSEL01 register setting. 0x0090 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 677 [PWM] Duty setting register 1 BT1PRLL BT1PRLH [PPG] H width setting reload register 1 [PWC] [PWC] [PWC] Data buffer register 1 Reserved BT1DTBF I/O selection register 0x009C BTSEL01 Reserved BTSSSR Simultaneous software activation register CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 678: Common Registers
Base Timer 19.4.1 Common Registers This section explains the common registers of the base timer. The registers described here are common to various operations. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 679 BTxTMR: Address Base_addr + 00 (Access: Half-word) bit15 bit14 - - - bit2 bit1 bit0 D[15:0] Initial value - - - Attribute R,WX R,WX - - - R,WX R,WX R,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 680 (*1) Attribute assumed for "Reserved" (*2) Attribute assumed for a 32-bit timer serving an odd-numbered channel (*3) Attribute assumed for a 32-bit timer serving an odd-numbered channel or for a 16/32-bit PWC timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 681 If "1" is written to the STRG bit or an external activation trigger (TGIN signal) is detected, this bit sets whether or not to recount the value of cycle setting register (BTxPCSR)/L width setting reload register (BTxPRLL) by reloading it to the 16-bit down counter. RTGEN Description of operation Does not reactivate Reactivates CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 682 [Reload timer/PWM/PPG] [bit9, bit8] EGS[1:0] (EdGe Select) : Trigger input selection bits Select an effective edge for the external activation trigger (TGIN) signal. EGS[1:0] Description Trigger input has no effect on the operation Rising edge Falling edge Both edges CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 683 Change this bit after changing the FMD[2:0] to 000.(Once you have changed the FMD[2:0] to 000, set the T32 bit and FMD[2:0] to a required value at the same time.) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 684 Reload mode: When the down counter underflows, the value of the base timer x cycle setting register (BTxPCSR) is reloaded to continue counting. One-shot mode: Once the down counter underflows, the counter will no longer count. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 685 This bit in odd-number channel is cleared to "0" when even-number channel outputs a falling edge during timer operation in the I/O modes 4 and 6. CTEN Description Read Write Under stopping This bit cleared to "0" Under operation This bit set to "1" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 686 When writing to this bit, be careful not to clear other bits.  When writing to CTEN and FMD[2:0] simultaneously, issue a trigger as soon as the operation is enabled. STRG Description Ignores. Issues a trigger. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 687 (Timer activation/stop mode) I/O mode 5 0101 (Simultaneous software activation mode) I/O mode 6 0110 (Software activation timer activation/stop mode) I/O mode 7 0111 (Timer activation mode) 1xxx Setting is prohibited CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 688 These bits are the input signal in the I/O modes 5 and 6. For the connections, see Figure 19-3. SSSR0/1 Description No effect on the operation. "1" pulse to the timer input, then the corresponding channel is activated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 689: Registers For 16/32-Bit Reload Timer
This section explains registers for 16/32-bit reload timer. 19.4.2.1 Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control) 19.4.2.2 Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse Counter Start Register) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 690 "1" and the UDIE bit is set to "1", an underflow interrupt request is generated. TGIR/UDIR Read Write No trigger detection/underflow occurred. This bit is cleared. Trigger detection/underflow occurred. No effect on the operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 691 For this reason, in the 32-bit timer mode, write values into these registers in the following order. Odd-number channel base timer x cycle setting register (BTxPCSR) Even-number channel base timer x cycle setting register (BTxPCSR) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 692: Registers For 16-Bit Pwm Timer
19.4.3.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control) 19.4.3.2 Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse Counter Start Register) 19.4.3.3 Duty Setting Registers 0, 1 : BTxPDUT (Base Timer 0/1 Pulse DuTy register) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 693 This bit indicates that a 16-bit PWM timer activation trigger is detected. When this bit is "1" and the TGIE bit is set to "1", a trigger interrupt request is generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 694 TGIR/DTIR/UDIR Read Write A trigger detection, duty match and underflow This bit is cleared. did not occur. A trigger detection, duty match or underflow No effect on the operation. occurred. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 695 (TOUT) can be fixed. The output signal level is as follows according to the setting of the OSEL bit of the base timer x timer control register (BTxTMCR):  OSEL= 0: "H" level  OSEL= 1: "L" level CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 696 (TOUT) can be fixed. The output signal level is as follows according to the setting of the OSEL bit of the base timer x timer control register (BTxTMCR):  OSEL= 0: All "H" level  OSEL= 1: All "L" level CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 697: Registers For 16-Bit Ppg Timer
19.4.4.2.L Width Setting Registers 0, 1 : BTxPRLL (Base Timer 0/1 Pulse Length of "L" register) 19.4.4.3.H Width Setting Registers 0, 1 : BTxPRLH (Base Timer 0/1 Pulse Length of "H" register) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 698 ". When this bit is "1" and the UDIE bit is set to "1", an underflow interrupt request is generated. TGIR/UDIR Read Write No trigger detection/underflow occurred. This bit is cleared. Trigger detection/underflow occurred. No effect on the operation. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 699 The value set to registers is loaded to the 16-bit down counter when a 16-bit PPG timer activation trigger is detected or when the base timer x H width setting reload register (BTxPRLH) completed counting values and underflows. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 700 When counting down from the value of the base timer x L width setting reload register (BTxPRLL) is completed. For rewriting timing, see "Write Timing" in "19.5.6.3 Operation in Reload Mode". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 701: 16/32-Bit Pwc Timer Register
This section explains registers for 16/32-bit PWC timer. 19.4.5.1.Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control) 19.4.5.2.Data Buffer Registers 0, 1 : BTxDTBF (Base Timer 0/1 DaTa BuFfer register) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 702 This bit indicates that the measurement of the 16/32-bit PWC timer is completed. When this bit is "1" and the EDIE bit is set to "1", a measurement completion interrupt request is generated. This bit is cleared when the measurement result (BTxDTBF) is read out. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 703 EDIR/OVIR Read Write Measurement completion/overflow has not been (EDIR) No effect on the operation. occurred. (OVIR) This bit is cleared. Measurement completion/overflow has been occurred. No effect on the operation. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 704 Value of odd-number channel data buffer register (BTxDTBF): Value of upper 16-bit In the 32-bit timer mode, read these registers value in the following order. Even-channel data buffer register (BTxDTBF) Odd-channel data buffer register (BTxDTBF) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 705: Operation
19.5.1 Selection of Timer Function 19.5.2 I/O Allocation 19.5.3 32-bit Mode Operation 19.5.4 16/32-bit Reload Timer Operation 19.5.5 16-bit PWM Timer Operation 19.5.6 16-bit PPG Timer Operation 19.5.7 16/32-bit PWC Timer Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 706: Selection Of Timer Function
Base Timer 19.5.1 Selection of Timer Function This section explains selection of the timer function. Select the timer function for BTxTMCR:FMD[2:0]. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 707: I/O Allocation
Activation of the odd-number channel is controlled by the even-number channel in this mode. The odd-number channel is started with the rising edge(*) of the output signal from the even-number channel. (*): Make a setting using the trigger input selection bit (BTxTMCR:EGS). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 708 TOUT TIOAm Block diagram for I/O mode 4 (Timer activation/stop mode) COU T DTRG TIOB n Base timer TGIN ch.n TOUT TIOAn TIOB m TGIN Base timer ch.m TOUT TIOAm CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 709 Block diagram for I/O mode 7 (timer activation mode) COUT EC K TIOB n Base timer TGIN ch. n TOUT TIOAn EC K TIOB m Base timer TGIN ch. m TOUT TIOAm CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 710: 32-Bit Mode Operation
This section explains the 32-bit mode operation. The reload timer and PWC timer can be operated in the 32-bit mode using two channels. The basic function/operation in the 32-bit mode is shown below. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 711 The upper 16-bit timer counter value of the odd-number channel is also loaded when the lower 16-bit timer counter value of the even-number channel is read. Thus, the timer counter value in operation can also be read. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 712 To transit from the 32-bit mode to the 16-bit mode, set "000" to the FMD bits of the BTxTMCR register of the even-number channel to reset to the reset mode for both the even-number and odd-number channels, and make a setting in the 16-bit mode for each channel. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 713 (excepting the cycle setting register for the reload timer) is ignored. Timer activation, waveform output and interrupt signal also apply the setting of the even-number channel. (The odd-number channel is masked with the value fixed to L.) For the configuration, see Figure 19-12 Figure 19-29. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 714: 16/32-Bit Reload Timer Operation
CTEN source Trigger generation Edge interrupt request detection Timer enabled IRQ1 CTEN TGIE BTxTMR : Base timer x timer register (BTxTMR) BTxPCSR : Base timer x cycle setting register (BTxPCSR) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 715 BT1PCSR : Base timer 1 cycle setting register (BT1PCSR) BT1TMR : Base timer 1 timer register (BT1TMR) BT0PCSR : Base timer 0 cycle setting register (BT0PCSR) BT0TMR : Base timer 0 timer register (BT0TMR) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 716 Reload mode (MDSE = 0): In this mode, when the down counter underflows, the preset value (cycle) is reloaded to allow the timer to restart counting.  One-shot mode (MDSE = 1): Once the down counter underflows, the counter will no longer count. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 717  If a software trigger is input: 1T (T: Count clock cycle)  If an external activation trigger (TGIN signal) is input: 2T to 3T (T: Count clock cycle) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 718 UDIE bit is set to "1". Figure 19-8 shows the operation in case of an underflow. Figure 19-8. Operation in Case of an Underflow Load Count clock Reload value Counter value Underflow UDIR CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 719 Figure 19-9. Output Waveform in Reload Mode (Normal Polarity) CTEN bit Opposite (Inversion) level when OSEL=1 O A0, TIOA1 pins Activation trigger Underflow CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 720 (BTxSTC) is set to "1". Figure 19-10 shows the operation in case of an underflow. Figure 19-10. Operation in Case of an Underflow Load Count clock 0000 Reload value Counter value Underflow UDIR CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 721 Figure 19-11. Output Waveform in One-shot Mode (Normal Polarity) CTEN bit Opposite (Inversion) level when OSEL=1 TI O A0 , TIOA1 pins Activation trigger Underflow Waiting for activation trigger CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 722 When the down counter underflows, the UDIR bit of the base timer x timer control register (BTxTMCR) of the even- number channels changes to "1". The channel configuration in 32-bit timer mode is shown below. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 723 In 32-bit timer mode, the operation of the 32-bit reload timer conforms to the settings of the even-number channels. Therefore, activation triggers and interrupt requests from even-number channels are valid. The output signal (TOUT) from an odd-number channel pin is fixed to "L" level. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 724 Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (ICR00 to ICR47). For information on interrupt level setting, see the chapter entitled "Chapter: Interrupt Control (Interrupt Controller)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 725 If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 726: 16-Bit Pwm Timer Operation
(TGIN signal) IRQ1 Trigger Edge CTEN detection Timer enabled Trigger interrupt request TGIE BTxPCSR: Base timer x cycle setting register (BTxPCSR) BTxPDUT: Base timer x duty setting register (BTxPDUT) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 727 Reload mode (MDSE = 0): In this mode, when the 16-bit down counter underflows, the preset cycle is reloaded to allow the timer to restart counting.  One-shot mode (MDSE = 1): Once the 16-bit down counter underflows, the counter will no longer count. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 728 The UDIR bit of the status control register (BTxSTC) changes to "1" and the level of the output signal (TOUT) is inverted.  The value of the cycle setting register (BTxPCSR) is reloaded to continue countdown. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 729 T : Cycle of count clock Note: If the count timing of the 16-bit down counter and the load timing occur at the same time, the load operation is given precedence. Output Waveform CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 730 If the duty value is set to the cycle setting value when a duty match interrupt request is generated, the output signal will be fixed to the " H" level in the next cycle. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 731 XXXX 0003 0002 0001 0000 0003 0002 PWM output waveform Interrupt request Activation edge Duty match Underflow trigger interrupt interrupt request interrupt request request (TGIR bit) (DTIR bit) (UDIR bit) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 732 If reactivation is permitted (RTGEN = 1): The TGIR bit of the base timer x status control register (BTxSTC) changes to "1". In addition, the value set in the base timer x cycle setting register (BTxPCSR) is reloaded to the 16-bit down counter, which begins counting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 733 It is the same operation as in reload mode. See "Output Waveform" in "19.5.5.2 Operation in Reload Mode". Interrupt Generation Timing It is the same operation as in reload mode. See "Interrupt Generation Timing" in "19.5.5.2 Operation in Reload Mode". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 734 Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (ICR00 to ICR47). For information on interrupt level setting, see the chapter entitled "Chapter: Interrupt Control (Interrupt Controller)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 735 If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 736: 16-Bit Ppg Timer Operation
Timer enabled TGIE BTxPRLL : Base timer x L width setting reload (BTxPRLL) BTxPRLH : Base timer x H width setting reload (BTxPRLH) BTxTMR : Base timer x timer register (BTxTMR) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 737 Reload mode (MDSE = 0): A sequence of "L"-level and "H"-level signals (consecutive pulses) is output.  One-shot mode (MDSE = 1): A string of one "L"-level signal and one "H"-level signal (single pulses) is output. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 738 ", the pulse width will be equal to one cycle of the count clock. When they are set to "FFFF ", the pulse width will be equal to 65536 cycles of the count clock. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 739 The output signal (TOUT) is at the "L" level. In addition, the value of the H width setting reload register (BTxPRLH) is transferred to the buffer. Steps 2 to 5 are repeated to continue counting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 740 : Value of base timer x L width setting reload register (BTxPRLL) n : Value of base timer x H width setting reload register (BTxPRLH) T : Count clock cycle CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 741 (BTxPRLH) during the period from the time an underflow occurs (the UDIR bit of the status control register (BTxSTC) changes to "1") to the time counting based on the next cycle begins. The new data will be effective as the next cycle. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 742 An example of interrupt request generation timing using the following settings is shown below.  Value of L width setting reload register (BTxPRLL) = 0001  Value of H width setting reload register (BTxPRLH) = 0001 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 743 Count clo ck XXXX 0001 0000 0001 0000 0001 0000 Counter value PPG output waveform Interrupt request Underfl o w interrupt Activation edge request (UDIR bit) trigger interrupt request (TGIR bit) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 744 If reactivation is permitted (RTGEN = 1): The TGIR bit of the status control register (BTxSTC) changes to "1". In addition, the value of L width setting reload register (BTxPRLL) is reloaded to the 16-bit down counter, which starts counting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 745 (2) = : Value of base timer x L width setting reload register (BTxPRLL) : Value of base timer x H width setting reload register (BTxPRLH) : Count clock cycle CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 746 (BTxPRLL) is loaded to the 16-bit down counter, which starts counting. Interrupt Generation Timing It is the same operation as in reload mode. See "Interrupt Generation Timing" in "19.5.6.3 Operation in Reload Mode". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 747 Set an interrupt level corresponding to the interrupt vector number, using interrupt control registers (ICR00 to ICR47). For information on interrupt level setting, see the chapter entitled "Chapter: Interrupt Control (Interrupt Controller)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 748 If an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur at the same time, the flag clear instruction is ignored. The interrupt request flag is held to "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 749: 16/32-Bit Pwc Timer Operation
Measurement factor (TIN signal) completion generation interrupt request Edge IRQ1 Activation detection detection IRQ 1 CTEN Edge EDIE detection Stop detection BTxDTBF : Base timer x data buffer register (BTxDTBF) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 750 Activation IRQ1 detection CTEN Edge EDIE detection Stop detection BT0DTBF : Base timer 0 x data buffer register (BT0DTBF) BT1DTBF : Base timer 1 x data buffer register (BT1DTBF) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 751  Single measurement mode (MDSE = 1): In this mode, measurement is conducted only once. Differences between the single and continuous measurement modes are listed on the table below. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 752 After measurement: The measurement After measurement: The measurement result is held. result is held. During overflow The measurement stops. The measurement restarts from 0x0000 Figure 19-26 shows the standard operation flow. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 753 Base Timer Figure 19-26. Operation Flow CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 754 Width Measurement of L pulse width(EGS2 to EGS0=100) Count start Count start Count stop Count stop Count (measurement) start: at falling edge detection Count (measurement) stop: at rising edge detection CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 755 Note: The input method of waveforms to be measured (TIN signal) varies depending on the I/O mode that has been set by the I/O selection register (BTSEL01). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 756 The current status waiting for a measurement start edge is continued. If the timer is reactivated during measurement: The up counter value is cleared to "0000 " and set to the measurement start edge waiting status. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 757 After the measurement, the measurement result can be read from the base timer x data buffer register (BTxDTBF) and the measured pulse width can be calculated using the following formula. Pulse width = n × T n: Data buffer register (BTxDTBF) value T: Count clock cycle CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 758 (BTxDTBF) of the even-numbered channel. Also, the upper 16-bit data is stored in the data buffer register (BTxDTBF) of the odd-numbered channel. The channel configuration in 32-bit timer mode is shown below. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 759  In 32-bit timer mode, the operation of the 32-bit PWC timer conforms to the settings of the even-number channel. Therefore, an interrupt request of the even-numbered channel is effective. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 760 Set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (ICR00 to ICR47). For information on interrupt level setting, see the chapter entitled "Chapter: Interrupt Control (Interrupt Controller)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 761 Pulse width continuous measurement mode: The timer reactivates and waits for a measurement start edge. The measurement end interrupt request flag (EDIR) is set to "1", and the currently measured result is transferred to the data buffer register (BTxDTBF). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 762: Reload Timer
20. Reload Timer This chapter explains the reload timer. 20.1 Overview 20.2 Features 20.3 Configuration 20.4 Registers 20.5 Operation 20.6 Application Note CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 763: Overview
Figure 20-1. Block Diagram of Reload Timer (1 Channel, Overview) Cascading to next reload timer Peripheral clock (PCLK) Prescaler TTRG external pin Counter TOUT external pin & Control unit Cascading from previous Interrupt reload timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 764: Features
 Single one-shot operation  Dual one-shot operation  Single reload operation  Dual reload operation  Compare mode  Capture mode (only software trigger)  Underflow interrupt/capture interrupt/compare interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 765 Use ch.0 output for ch.1 input. Use ch.1 output for ch.2 input. Use ch.2 output for ch.3 input. Use ch.4 output for ch.5 input. Use ch.5 output for ch.6 input. Use ch.6 output for ch.7 input. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 766: Configuration
Select CSL0 GATE Prescaler Gate Edge control control Peripheral TRGM1 clock Input TTRG Select TRGM0 S yn ch ro n iza tio n Peripheral clock TMCSR bit in any sequence CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 767: Registers
TMRLRA2 TMR2 16-bit timer register 2 16-bit timer reload register B2 0x010C TMRLRB2 TMCSR2 Control status register 2 16-bit timer reload register A3 0x0110 TMRLRA3 TMR3 16-bit timer register 3 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 768 16-bit timer reload register A10 0x01D0 TMRLRA10 TMR10 16-bit timer register 10 16-bit timer reload register B10 0x01D4 TMRLRB10 TMCSR10 Control status register 10 *1: CY91F59A/B only supports (reserved for the others) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 769: Control Status Register : Tmcsr (Timer Control And Status Register)
Select an effective external edge which can be a reload trigger through TTRG input in the following manner: TRGM[1:0] TTRG effective external edge No external trigger detection (initial value) Rising edge Falling edge Both edges CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 770 Division of the peripheral clock frequency by 64 Cascade mode (ch.0:TTRG0, ch.1:TOUT0, ch.2:TOUT1, ch.3:TOUT2 ch.4:TTRG7, ch.5:TOUT7, ch.6:TOUT8, ch.7:TOUT9) Event counter mode External event (TTRG input) *1: ch.4, 5, 6, and 7 are only supported by CY91F59A/B CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 771 * : However, the dual one-shot function reloads TMRLRB at the same time as TMRLRA underflow and continues counting. After that, count operation stops at the same time as TMRLRB underflow. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 772 Trigger input through this register is effective only when bit1:CNTE =1. Writing "1" into the TRG bit always generates an effective trigger if the timer is activated (bit1:CNTE=1) in any operation mode. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 773: 16-Bit Timer Register : Tmr (16Bit Timer Register)
R,WX ..R,WX R,WX R,WX [bit15 to bit0] TMR[15:0] (TiMeR) : 16-bit timer This register can be read the counter value of the 16-bit timer. The initial value is undefined. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 774: 16-Bit Timer Reload Register A, 16-Bit Timer Reload Register B : Tmrlra, Tmrlrb
RELD (bit4 of the TMCSR register), and OUTL (bit5 of the TMCSR register) bit setting as well as the TMRLRA/B register value. H width and L width setting of the waveform(TOUT) to be outputted is shown in the table below. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 775 TOUT = (Setting value of this register + 1) × count source cycle * : The formula described above is effective only in the interval timer mode. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 776: Operation
Reload Timer 20.5 Operation This section explains the operation of the reload timer. 20.5.1 Setting 20.5.2 Operation Procedure 20.5.3 Operations of Each Counter 20.5.4 Cascade Input 20.5.5 Priority of Concurrent Operations CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 777: Setting
20.5.1 Setting Setting of the reload timer is shown below. The operation of this timer is set based on the "count source" (select in the TMCSR:CSL[2:0]) and counter operation ({TMCSR:MOD[1:0], TMCSR:RELD}). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 778 Division of the peripheral clock frequency by 64 Cascade mode (ch.0:TTRG0, ch.1:TOUT0, ch.2:TOUT1, ch.3:TOUT2 ch.4:TTRG7, ch.5:TOUT7, ch.6:TOUT8, ch.7:TOUT9) Event counter mode External event (TTRG input) *1: ch.4, 5, 6, and 7 are only supported by CY91F59A/B. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 779 "reload register setting value + 1" count. The timer underflow period, TUF, in the interval timer mode can be represented as follows: TUF = Peripheral clock (PCLK) period × prescaler division value (2-64) × (Reload register value (TMRLRA/B) + 1) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 780 The TTRG pin is used as a count source in the event counter mode. Hence, a software trigger is always used. In the interval timer mode, settings are made in the TMCSR register. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 781 TTRG external pin. Table 20-4. TTRG Effective Level TRGM[0] TTRG Effective Level TTRG pin "L" counted only during the input period (initial value) TTRG pin "H" counted only during the input period CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 782 Reload TMRLRA and TMRLRB in turns Dual reload Stop the counter with 0xFFFF Compare one-shot Reload TMRLRA Compare reload Stop the counter with 0xFFFF Capture one-shot Reload TMRLRA Capture reload CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 783 A/B of the section of the UF (underflow) below indicates whether down counting underflow has occurred with a value when loading TMRLRA data or TMRLRB data. CMP (compare-match) shows the timing of down counting from TMRLRB = TMR. Figure 20-3. OUT Output Change in Each Event (1 / 3) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 784 Reload Timer Figure 20-4. TOUT Output Change in Each Event (2 / 3) Figure 20-5. TOUT Output Change in Each Event (3 / 3) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 785: Operation Procedure
Reload Timer 20.5.2 Operation Procedure Operation procedures are shown. 20.5.2.1. Activation 20.5.2.2. Retrigger 20.5.2.3. Underflow/Reload 20.5.2.4. Generation of Interrupt Requests 20.5.2.5. Concurrent Operation of Register Write and a Timer Activation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 786 TTRG input in the effective input polarity waiting, the timer initiates down count operation. For TTRG, input pulse of 2 × T (T indicates the peripheral clock (PCLK) cycle) or more. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 787 Timer Activation (when the trigger input function and the rising edge trigger are selected) Peripheral clock CNTE (register) TRG (register) Prescaler clear Prescaler clock Data load TTRG (Pin) Reload data Counter value Timer Activation (when in the gate input function) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 788 Only in the capture mode, retrigger generation transfers a value being counted to the TMRLRB to set the EF bit of the TMCSR register. Note: TOUT is not initialized in the one shot mode at retrigger. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 789 TTRG(pin) CNTE(register) Prescaler clear Reload data Count value Reload data TRG(register) Retrigger TOUT (When OUTL=0) One-shot mode Retrigger Operation (TTRG is gate input, count when in H level, one-shot output) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 790 Underflow is defined as the timer down-counting from 0x0000. When underflow occurs, the bit2:UF bit of the TMCSR register is set. Underflow takes place in the timer if the count value reaches "reload register setting value + 1" count. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 791 Figure 20-8. Example of UF Interrupt Request Output Operation Count clock Counter value 0x0001 0x0000 Reload data Underflow UF bit Interrupt request UF interrupt request output operation (bit4:RELD= "1" and bit3:INTE="1" of TMCSR register) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 792 Setting of the EF bit (Writing "0" is ignored) Reloading old data Writing to the reload register Loading of timer by retrigger (The written value will be loaded next time) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 793: Operations Of Each Counter
Operations of each counter are shown. 20.5.3.1 Single One-shot Operation 20.5.3.2 Single Reload Operation 20.5.3.3 Dual One-shot Operation 20.5.3.4 Dual Reload Operation 20.5.3.5 Compare One-shot Operation 20.5.3.6 Compare Reload Operation 20.5.3.7 Capture Mode CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 794  Timer is waiting for a trigger. For the single one-shot timer, TMRLRA turns to the initial value of the counter when a reload took place. TMRLRB is not used. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 795 (when OUTL=0) CNTE (register) TTRG (pin) TRG (register) waiting for trigger Count operation waiting for effective gate input TMRLRA+1 counting Single One-shot timer GATE="1" gate input, TRGM "H" input interval counting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 796 Sets bit2:UF bit of the TMCSR register.  When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.  Loads TMRLRA register onto the counter.  Inverts TOUT output.  Continues decrementing count. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 797 TOUT (When OUTL=0) TTRG(pin) CNTE(register) Data load TRG(register) Waiting for activation trigger Count operation waiting for effective gate input Single reload function (GATE="1": gate input, TRGM: H input interval count) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 798  When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.  Stops the count with 0xFFFF.  Initializes TOUT output.  Timer is waiting for an activation trigger. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 799 Waiting for count count activation trigger activation trigger Timer reloaded TMRLRA TMRLRA TMRLRB TMRLRB register A:TMRLRA Counter value A -1 -1 -1 0xFFFF A -1 B:TMRLRB Dual one-shot operation (gate input) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 800 Sets bit2:UF bit of the TMCSR register.  When interrupts are enabled (bit3:INTE=1 of TMCSR register), an interrupt occurs.  Loads TMRLRA to the counter.  Inverts TOUT output.  Starts a down count from TMRLRA. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 801 CNTE(register) Data load TRG(register) Waiting for activation trigger Waiting for effective gate input Count from TMRLRA Count from TMRLRB Dual Reload function (GATE=1 : gate input, H input interval count) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 802  The timer stops with 0xFFFF.  Timer is waiting for an activation trigger. The operation of the compare function changes depending on the setting relation between TMRLRA and TMRLRB. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 803 L level (for OUTL="0"). Count clock Register reloaded TMRLRA TMRLRA by timer Underflow TOUT (for OUTL=0) TMRLRA+1 TMRLRA+1 Activation Activation trigger waiting trigger waiting Activation trigger Compare one-shot function (TMRLRB > TMRLRA) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 804 TMR. The level will remain to be L even when an underflow occurs (for OUTL="0"). Count clock Register reloaded TMRLRA TMRLRA by timer Underflow Activation Activation Activation trigger trigger waiting trigger waiting TOUT waiting TMRLRA+1 TMRLRA+1 (for OUTL=0) Activation trigger Compare one-shot function (TMRLRB="0") CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 805  Initializes TOUT output.  Reloads a value from TMRLRA.  The timer continues to count. The operation of a compare feature depends on the relationship between TMRLRA and TMRLRB. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 806 TMRLRA and continue counting operation (for OUTL="0"). Count clock Register TMRLRA TMRLRA TMRLRA reloaded by timer Underflow UF bit TOUT (for OUTL=0) TMRLRA+1 TMRLRA+1 TMRLRA+1 Activation trigger Compare reload function (TMRLRB > TMRLRA) trigger input CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 807 TMR. The level will remain to be L even when an underflow occurs. Count clock Register TMRLRA TMRLRA TMRLRA reloaded by timer Underflow UF bit TOUT TMRLRA+1 TMRLRA+1 TMRLRA+1 (for OUTL=0) Activation trigger Compare reload function (TMRLRB = "0") trigger input CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 808 TOUT is not initialized in the one shot mode at retrigger. Figure 20-20. Operation of Capture Trigger input Retrigger input TMRLRA Underflow Underflow Capture TMR to TMRLRB UF interrupt EF interrupt & & Reload (TMRLRA) Capture (TMRLRB) & Reload (TMRLRA) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 809 Figure 20-21. Flowchart of Trigger Input Features in Interval Timer Mode GATE=0 AND CSL[2:0]=000 CNTE=1? TRG=1 or TTRG effective edge input Reloads to the timer Clock? Count-1 Underflow occurs? RELD = 1? CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 810 Reload Timer Figure 20-22. Flowchart in Event Counter Mode CSL [2:0] = 111 CNTE=1? TRG=1? Loads to the counter Valid event input? Count-1 Underflow occurs? RELD = 1? CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 811: Cascade Input
Timer ch.5 Timer ch.6 TOT4 TIN5 TOT5 TIN6 (6) Use ch.7 in cascade settings. Timer ch.6 Timer ch.7 TOT6 TIN7 *1: ch.4, 5, 6, and 7 are only supported by CY91F59A/B. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 812: Priority Of Concurrent Operations
When a set of each flag by the timer operation and a clear of a flag by register write occur concurrently, the priority of deciding the operation is indicated. Setting flag by the timer operation Writing to a register for a clear of flag to the UF bit/EF bit CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 813: Application Note
TMRLRA0 TMRLRA Interrupt can be generated CNT_a CNT_b TMRLRB register Note: When the rising edge is specified as effective edge. Following are some configurations for use of example figure above. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 814 (Single mode) Reload timer Mandatory (Single mode) 0 or 1 Mandatory Mandatory (Programmable Pulse Generator) (Dual mode) Mandatory Mandatory (Pulse Width Modulator) (Compare mode) Mandatory (Pulse Width Counter) (Capture mode) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 815: Single One-Shot Timer
*2: TOUT output polarity setting OUTL=0------Initial value L=> Count starts H=> Underflow occurs L OUTL=1------Initial value H=> Count starts L=> Underflow occurs H *3: Interrupt request enable setting INTE=0------Interrupt disabled INTE=1------Interrupt enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 816 CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8 CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16 CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32 CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 817 Input an effective level when you use TTRG pin input as the gate input Figure 20-25. Example of Operation (OUTL = 0) TOUT (TMRLRA + 1) Counter value TMRLRA 0x0000 0xFFFF Activation trigger Underflow Downcount CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 818: Reload Timer
OUTL=0------Initial value L=> Count starts L=> Invert whenever an underflow occurs OUTL=1------Initial value H=> Count starts H=> Invert whenever an underflow occurs *3: Interrupt request enable setting INTE=0------Interrupt disabled INTE=1------Interrupt enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 819 OUTL=0------Initial value L=> Count starts L=> Invert whenever an underflow occurs OUTL=1------Initial value H=> Count starts H=> Invert whenever an underflow occurs *4: Interrupt request enable setting INTE=0------Interrupt disabled INTE=1------Interrupt enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 820 Input an effective level when you use TTRG pin input as the gate input Figure 20-26. Example of Operation (OUTL=0) TOUT (TMRLRA + 1) (TMRLRA + 1) Counter value TMPLRA 0x0000 TMRLRA 0x0000 TMRLRA Activation trigger Underflow Downcount CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 821: Ppg
TMRLRA, and outputs the "H level" while counting until the occurrence of an underflow caused by the down count from TMRLRB. When a retrigger occurs, TOUT output returns to its initial value. Note: TOUT is not initialized in the one shot mode at retrigger. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 822 Count L from TMRLRB => H when an underflow occurs *3: Reload setting when an underflow occurs RELD= 0------One-shot mode RELD= 1------Reload mode *4:Interrupt request enable setting INTE= 0------Interrupt disabled INTE= 1------Interrupt enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 823 Initial value H=> Count H from TMRLRA => L when an underflow occurs => Count L from TMRLRB => H when an underflow occurs *4:Reload setting when an underflow occurs RELD=0------One-shot mode RELD=1------Reload mode *5:Interrupt request enable setting INTE=0------Interrupt disabled INTE=1------Interrupt enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 824 Input an effective level when you use TTRG pin input as the gate input Figure 20-27. Example of Operation (OUTL=0) TOUT (TMRLRA + 1) (TMRLRB + 1) Counter value TMPLRA 0000 TMRLRB 0x0000 TMRLRA Activation trigger Underflow Downcount CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 825: Pwm
INTE= 1------Interrupt enabled *5: To use TOUT output with L clip output, set to TMRLRB = 0. To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 826 INTE=1------Interrupt enabled *6: To use TOUT output with L clip output, set to TMRLRB = 0. To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 827 INTE= 1------Interrupt enabled *6: To use TOUT output with L clip output, set to TMRLRB = 0. To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 828 Input an activation trigger (a write of "1" to TRG bit or an input of effective external edge from TTRG pin)  Input an effective level when you use TTRG pin input as the gate input Figure 20-28. Example of Operation (OUTL=0) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 829: Pwc
T = (The set value for TMRLRA - The captured value for TMRLRB) × Peripheral clock (PCLK) cycle × Division ratio set with CSL CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 830 Reload Timer Figure 20-29. Example of Operation (TRGM=01) TTRG input Activation trigger TMRLRA CNT_A TMRLRA Counter value (reload) (reload) TMRLRA CNT_B Retrigger input TMRLRB 0xXXXX CNT_A CNT_B Downcount CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 831 Reload Timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 832: Free-Run Timer
21. Free-Run Timer This chapter explains the free-run timer. 21.1 Overview 21.2 Features 21.3 Configuration 21.4 Registers 21.5 Operation 21.6 Setting 21.7 Q&A 21.8 Sample Program 21.9 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 833: Overview
Figure 21-1. Block Diagram (Overview) To output compare External clock Peripheral clock (FRCK pin) (PCLK) To input capture Overflow Clear Up counter Compare circuit Compare clear register Interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 834: Features
If there is a compare match with reset, software clear or compare clear register, the counter value will be reset to "00000000 ".  It is used as the reference count for output compare and input capture. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 835: Configuration
Free-run timer 2 and 3 of CY91F591/2/4/6/7/9 are used as input capture for LSYN only. Therefore, they do not cooperate with output compare. Also, no external clock is provided to support them (During clock selection, selecting "External clock" is disabled). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 836: Registers
Timer control register low-order 5 0x04A8 CPCLR6 Compare clear register 6 0x04AC TCDT6 Timer data register 6 Timer control register high-order 6 0x04B0 TCCSH6 TCCSL6 Reserved Timer control register low-order 6 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 837 Registers Address Register function 0x04D0 CPCLR7 Compare clear register 7 0x04D4 TCDT7 Timer data register 7 Timer control register high-order 7 0x04D8 TCCSH7 TCCSL7 Reserved Timer control register low-order 7 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 838: Timer Control Register (Upper Bit) : Tccsh
Note: The setting change for the count clock selection bit must be performed while other peripheral modules using the free-run timer output (output compare and input capture) are inactive. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 839 ICRE Operation Interrupt disabled Interrupt enabled  When the ICRE bit and compare clear interrupt flag bit (ICLR) are set to "1", an interrupt request for CPU will be generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 840: Timer Control Register (Lower Bit) : Tccsl
If output compare is in use, the output compare operation will stop when the free-run timer stops. [bit5] - : Undefined The read value is always "0". This does not affect the writing operation. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 841 (output compare and input capture) using the free-run timer output are inactive.  When the free-run timer is used as compare data for the output compare, the free-run timer clock frequency cannot be set as CLK[3:0]= 0000 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 842: Compare Clear Register : Cpclr
(the STOP bit of timer state control register lower (TCCSL) = 1).  Writing to this register during operation will have no meaning.  When accessing this register, use a word access instruction. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 843: Timer Data Register : Tcdt
The Clear bit (SCLR = 1) of the timer state control register (TCCSL)  The timer count value matches the compare clear register  Writing to this register while it is in operation will have no meaning. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 844: Operation
This section explains the operations of the free-run timer. 21.5.1 Count Operation of the Free-run Timer 21.5.2 Counting Up 21.5.3 Timer Clear 21.5.4 Each Clear Operations of the Free-run Timer 21.5.5 Timer Interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 845: Count Operation Of The Free-Run Timer
(2) Clearing of the free-run timer by reset (Count value "00000000 ") (3) Count up operation by the free-run timer (4) Compare clear match of the free-run timer and interrupt generation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 846 (7) The free-run timer counts up in the clock obtained by dividing the internal clock (count clock). (8) The free-run timer counts up in the count clock obtained by synchronizing the external clock with the internal clock. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 847: Counting Up
It continues to count up until the count value matches the value of the compare clear register (CPCLR). The counter will then be cleared to "00000000 " and start counting up again. Figure 21-3. Up Counter Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 848: Timer Clear
The counter will be cleared as soon as it has been reset. When there is a match with the compare clear register, the counter will be cleared in synchronization with the count timing. Figure 21-4. Clear Timing of the Free-run Timer  Compare clear register value Compare match 00000000 Count value CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 849: Each Clear Operations Of The Free-Run Timer
Operation Operation stop stop Timing of clearing by compare match “00000000” “00000001” N - 1 Count value Compare value=N Compare value Compare match Clearing free-run timer Interrupt request CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 850 (2) When "1" is written to SCLR: bit4 of the TCCSL register while it is in operation (3) When there is a match with the compare clear register (4) When "00000000 " is written to the TCDT register while it is in stop CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 851: Timer Interrupt
Compare clear interrupt The compare clear interrupt will be generated when the timer value matches the value of the compare clear register (CPCLR). Figure 21-5. Interrupt Count value Compare clear interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 852: Setting
Interrupt request enable Table 21-4. Settings Required for Stopping the Free-run Timer (n: channel number) Configuration Configured register Setting method Timer control registers Free-run timer stop bit setting 21.7.7 (TCCSLn) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 853: Q&A
21.7.3 How to Enable/Disable the Count Operation of the Free-run Timer 21.7.4 How to Clear the Free-run Timer 21.7.5 About Interrupt Related Registers 21.7.6 How to Enable Compare Clear Interrupt 21.7.7 How to Stop the Free-run Timer Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 854: How To Select Internal Clock Dividers
To select 32/F Set "0". Set "0101". PCLK To select 64/F Set "0". Set "0110". PCLK To select 128/F Set "0". Set "0111". PCLK To select 256/F Set "0". Set "1000". PCLK CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 855: How To Select The External Clock
(See "Chapter: I/O Ports".) Note: No external clock is provided to support free-run timer 2 (only for LSYN) and 3 (only for LSYN) of CY91F591/2/4/6/7/9 (During clock selection, selecting "External clock" is disabled). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 856: How To Enable/Disable The Count Operation Of The Free-Run Timer
This section explains how to enable/disable the count operation of the free-run timer. Set the count operation bits (TCCSLn:STOP). (n: channel number) Operation Count operation bit (STOP) To operate the free-run timer Set "0". To stop the free-run timer Set "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 857: How To Clear The Free-Run Timer
Overflow of the free-run timer will result in the count value returning to "00000000 ".  It will be cleared if there is a match with the compare clear register. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 858: About Interrupt Related Registers
Since interrupt request flags (TCCSHn:ICLR) will not be cleared automatically, clear the flags using software before returning from interrupt processing. (Write "0" to the ICLR bit) (n: channel number) *1: ch.2 and 3 of CY91F591/2/4/6/7/9 are used for LSYN only. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 859: How To Enable Compare Clear Interrupt
Set "1". Clearing of the interrupt request can be configured using interrupt flag bits (TCCSHn:ICLR). (n: channel number) Operation Compare clear interrupt flag bit (ICLR) Interrupt request clear Write "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 860: How To Stop The Free-Run Timer Operation
This section explains how to stop the free-run timer operation. Set using the count operation bits (TCCS0:STOP), (TCCS1:STOP), (TCCS2:STOP), (TCCS3:STOP). "21.7.3 How to Enable/Disable the Count Operation of the Free-run Timer". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 861: Sample Program
<Interrupt vector> Vector table setting (Note) Clock-related settings and the setting of __set_il (numeric value) need to be configured in advance. See “Chapter: Clock” and “Chapter: Interrupt Control (Interrupt Controller)” CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 862: Notes
(external clock) must at least be input after the compare match. Read-modify-write  Compare clear interrupt flag bits of the timer control register are "1" when read using a read-modify-write instruction. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 863 Free-Run Timer CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 864: Output Compare
22. Output Compare This chapter explains the output compare. 22.1 Overview 22.2 Features 22.3 Configuration Diagram 22.4 Registers 22.5 Operation 22.6 Setting 22.7 Q&A 22.8 Sample Program 22.9 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 865: Overview
Interrupts OCU0 Output compare 0 Latch Comp Toggle OCU1 Output Latch Comp Output compare 1 OCU2 Output compare 2 Latch Comp Toggle OCU3 Output Latch Comp Output compare 3 Interrupts CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 866: Features
Four compare registers can be used for independence.  Output pins and interrupt flags correspond to the compare register.  Output pins can be inverted with the use of two compare registers. (Function only for OCU1, OCU3) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 867 Output Compare  The initial value of each output pin can be set.  When the output compare register matches the 32-bit free-run timer, an interrupt can be generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 868: Configuration Diagram
Compare operation stop IOP1 OCSL01: bit7 Enable compare ope ration No interrupt request OCU3 interrupt Interrupt request IOE1 Write 0: Flag clear OCSL23: bit5 IOE1 OCSL01: bit5 Disable interrupt Enable interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 869: Registers
0x02F4 OCCP2 Compare register 2 0x02F8 OCCP3 Compare register 3 Free-run timer selection register 23 0x02FC OCFS23 Reserved OCSH23 OCSL23 Output control register 23 upper Output control register 23 lower CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 870: Free-Run Timer Selection Register : Ocfs
Writing to these bits does not affect the operation of the output compare. [bit1, bit0] SELn : Free-run timer selection SELn (n=0~3) Operating mode Free-run timer 0 Free-run timer 1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 871: Output Control Register (Upper Bit) : Ocsh
When the compare register 0, 1 and 2, 3 have the same value, the operation is the same one as when only one compare register is used. [bit11, bit10] Reserved Always set these bits to "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 872 When OCU0, OCU2 pins output is performed, the setting of a general-purpose port is required. The setting should be performed after the compare operation is stopped. With the reading operation, the output compare pin output is read. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 873: Output Control Register (Lower Bit) : Ocsl
This bit becomes "1" when the count value of free-run timer (TCDT) corresponds to the output compare compare register (OCCP0, OCCP2).  The interrupt request becomes enabled when the interrupt enable bit (IOE0, IOE2) is "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 874 The compare registers (OCCP0, OCCP2) must be set with values before the compare operation is enabled  Because the output compare is synchronized with the free-run timer, when the free-run timer is stopped, the output compare operation also is stopped. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 875: Compare Register : Occp
In addition, when the corresponding OCU of the port function register (PFR) is set and output is enabled, the output level corresponding to the compare register is inverted.  For access to this register, use a word access instruction. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 876: Operation
This section explains the operations of the output compare. 22.5.1 Output Compare Output (Independent Invert) CMOD = "0" 22.5.2 Output Compare Output (Coordinated Invert) CMOD = "1" 22.5.3 Output Compare Operation Timing CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 877: Output Compare Output (Independent Invert) Cmod = "0
(4) A free-run timer value is compared with a compare value and they match (Compare match) (5) OCU output level is inverted. (6) A compare match interrupt request is generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 878: Output Compare Output (Coordinated Invert) Cmod = "1
(7) Free-run timer count up (8) Compare 0 match (9) OCU0 output level is inverted. When CMOD = 1, OCU1 output level also is inverted. (10) Compare 0 match interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 879: Output Compare Operation Timing
The output compare can invert the output as well as generate an interrupt when the free-run timer value matches the specified compare register value and a compare match signal is generated. The output invert timing on compare match is synchronized with the counter count timing. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 880 A match signal is not generated Compare clear register 0 value Compare register 0 write Compare clear register 1 value Compare register 1 write Compare 0 stop Compare 1 stop CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 881 Output Compare 22.5.3.2 Compare match, Interrupt Compare match, interrupt are shown below. Figure 22-5. Compare match, Interrupt Timing CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 882 Output Compare 22.5.3.3 Pin Output This section shows the pin output. Figure 22-6. Pin Output Timing Counter value Value of Compare register Compare match Pin output CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 883: Setting
See "Chapter: Interrupt Control Interrupt Controller)". and output compare interrupt level Setting of output compare interrupt  Interrupt request clear Output control register (OCSHxx, OCSLxx) 22.7.10  Interrupt request enable CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 884: Q&A
How Can I Clear the Free-run Timer? 22.7.7 How Can I Enable the Compare Operation? 22.7.8 Interrupt Related Register? 22.7.9 Interrupt Type? 22.7.10 How Can I Enable the Interrupt? 22.7.11 Calculation Method for the Compare Value? CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 885: How Can I Set The Compare Value
Output Compare 22.7.1 How Can I Set the Compare Value? This section explains how to set the compare value. Write the compare value to the compare register OCCPx. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 886: How Can I Set The Compare Mode? (Example With Ocu1)
Regardless of the CMOD bit, the operation is as follows:  Regardless of the compare mode bit (OCSH01:CMOD) setting, the OCU0 output is inverted when the free-run timer value matches the compare register (OCCP0). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 887: How Can I Enable/Disable The Compare Operation? (Example With Ocu0, Ocu1)
Set (OCSL01:CST0) to "0". To stop (disable) the compare operation Compare 1 Set (OCSL01:CST1) to "0". Compare 0 Set (OCSL01:CST0) to "1". To enable the compare operation Compare 1 Set (OCSL01:CST1) to "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 888: How Can I Set The Compare Pin Output Initial Level? (Example With Ocu0, Ocu1)
To set the compare 0 pin to "H" Set (OCSH01:OTD0) to "1". To set the compare 1 pin to "L" Set (OCSH01:OTD1) to "0". To set the compare 1 pin to "H Set (OCSH01:OTD1) to "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 889: How Can I Set The Compare Pin Ocu0, Ocu1 For Output
22.7.5 How Can I Set the Compare Pin OCU0, OCU1 for Output? This section explains how to set the compare pin OCU0, OCU1 for output. Set the pin for peripheral output. For setting method, see "Chapter: I/O Ports". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 890: How Can I Clear The Free-Run Timer
This section explains how to clear the free-run timer. Set the clear bit (TCCSL:SCLR) of the free-run timer used. Operation Clear bit (SCLR) To clear the free-run timer Write "1". For other methods, see "Chapter: Free-Run Timer". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 891: How Can I Enable The Compare Operation
This section explains how to enable the compare operation. Set the compare operation enable bit (OCSL01:CST0, OCSL01:CST1, OCSL23:CST2, OCSL23:CST3). "22.7.3 How Can I Enable/Disable the Compare Operation? (Example with OCU0, OCU1)". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 892: Interrupt Related Register
Address: 0FFF10 Address: 0046B The interrupt request flag (OCSL01:IOP0, OCSL01:IOP1, OCSL23:IOP2, OCSL23:IOP3) are not cleared automatically. Before recovering from the interrupt process, write "0" to each bit to clear with software. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 893: Interrupt Type
Output Compare 22.7.9 Interrupt Type? This section explains the interrupt type. The interrupt has one type only. It is generated by a compare match. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 894: How Can I Enable The Interrupt
Set "1". Set the interrupt request flag bit (OCSL01:IOP0, OCSL01:IOP1, OCSL23:IOP2, OCSL23:IOP3) for the interrupt request clear. Interrupt request flag bit Operation (OCSL01:IOP0, OCSL01:IOP1, OCSL23:IOP2, OCSL23:IOP3) Interrupt request clear Write "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 895: Calculation Method For The Compare Value
Output Compare 22.7.11 Calculation Method for the Compare Value? This section explains the calculation method for the compare value. 22.7.11.1 Toggle Output Pulse 22.7.11.2 PWM Output CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 896 (Example) To calculate a two-phase pulse with OCU0, OCU1, cycle: A, and one-fourth phase difference  FreeRunTimer.CPCLR = (A/2) -1  Output Compare.OCCP0 = (A/2)×(3/4) -1  Output Compare.OCCP1 = (A/2)×(1/4) -1  Output Compare.OCSH01.CMOD = 0 are setting. OCU0 OCU1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 897 (Example) To calculate the PWM with OCU0, OCU1, cycle: A, and duty 1/4  FreeRunTimer.CPCLR = (A/2)-1  Output Compare.OCCP0 = (A/2)×(1/2) -1  Output Compare.OCCP1 = (A/2)×(1/4) -1  Output Compare.OCSH01.CMOD = 1 are setting. OCU1 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 898: Sample Program
4. Interrupt vector - Setting of the vector table (Note) Clock-related setting and setting of __set_il(numerical value) in advance are required. See “Chapter: Clock” and “Chapter: Interrupt Control (Interrupt Controller)”. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 899 4. Interrupt vector - Setting of the vector table (Note) Clock-related setting and setting of __set_il(numerical value) in advance are required. See “Chapter: Clock” and “Chapter: Interrupt Control (Interrupt Controller)”. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 900: Notes
) is disabled PCLK for the free-run timer clock frequency TCCSL:CLK[3:0]. Read-modify-write When the interrupt request flag bits (IOP0), (IOP1), (IOP2), (IOP3) are read with read-modify-write (RMW) instruction, "1" is read. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 901 Output Compare CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 902: Input Capture
23. Input Capture This chapter explains the input capture. 23.1 Overview 23.2 Features 23.3 Configuration 23.4 Registers 23.5 Operation 23.6 Setting 23.7 Q&A 23.8 Sample Program 23.9 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 903: Overview
Figure 23-1. Block Diagram LIN Sync Field detection Free-run timer Capture Buffer Edge detection circuit External pin ICU Interrupt CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 904: Features
Precision: Peripheral clocks (PCLK)/1,/2, /4, /8, /16, /32, /64, /128, /256) (count clock of the free-run timer) *1: Input captures 6 and 7 of CY91F591/2/4/6/7/9 are used for LSYN only. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 905: Configuration
Interrupt request From free-run timer WRITE 0: Flag clear Port reading Note: Input captures 6 and 7 of CY91F591/2/4/6/7/9 are for LSYN only. No external pin is provided to support them. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 906: Registers
0x0FD4 ICU7/ICU7_1 0x0FDC ICU8/ICU8_1 0x0FE0 ICU9/ICU9_1 0x0FE8 ICU10/ICU10_1 0x0FEC ICU11/ICU11_1 *1: ch.6 and 7 of CY91F591/2/4/6/7/9 are used for LSYN only. *2: ch.8 to 11 are only supported by CY91F59A/B. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 907 Input capture control register 89 0x0FE8 IPCP10 Input capture data register 10 0x0FEC IPCP11 Input capture data register 11 Free-run timer selection register 1011 0x0FF0 ICFS1011 Reserved ICS1011 Input capture control register 1011 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 908: Input Capture Data Register : Ipcp
X X X X X X X X X X X X Attribute R,WX Note: When accessing this register, use a word access instruction. No data can be written to this register. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 909: Free-Run Timer Selection Register : Icfs
― ― ― ― ― ― SEL9 SEL8 ― ― ― ― ― ― Initial value Attribute R1,WX R1,WX R1,WX R1,WX R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 910 This does not affect the writing operation. [bit1, bit0] SELn : Free-run timer selection SEL{0,1,2,3,4,5} Operation Free-run timer 0 Free-run timer 1 SEL{6,7,8,9,10,11} Operation Free-run timer 2 Free-run timer 3 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 911: Input Capture Control Register : Ics
(Input capture 8, 9): Address 0FE7 (Access: Byte, Half-word, Word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ICP9 ICP8 ICE9 ICE8 EG91 EG90 EG91 EG90 Initial value Attribute R(RM1),W R(RM1),W CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 912 These bits are used to select the capture effective edge(s) for the input capture signal from the external pin.  The input capture will be in stop if the effective edge selection bit is "00 ". * EGn1, EGn0: n corresponds to the input capture channel numbers. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 913: Lin Synch Field Switching Register : Lsyns
- : Undefined The read value is always "1". This does not affect the writing operation. [bit3, bit2] Reserved Always write "0" to these bits. The read value is "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 914 *1: ch.6 and 7 of CY91F591/2/4/6/7/9 are used for LSYN only. *2: ch.8 to 11 are only supported by CY91F59A/B. Note: The input for the input capture must be switched while the capture is inactive (ICS:EG[n1:n0]= 00). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 915: Operation
When a set effective edge is detected, the 32-bit input capture can retrieve the value of the 32-bit free-run timer into the capture register and generate an interrupt. This section explains the input capture operation. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 916: Capture And Interrupt Timings
This section explains capture and interrupts timings of the input capture. Input capture Peripheral Clock (PCLK) Valid Edge Free-run timer 0 Capture register Interrupt FFFFFFFF Count of free-run timer 00000000 Time Enable free-rum timer operation Input capture Interrupt request CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 917 (3) Free-run timer value is recorded to the capture register (capture). (4) Input capture interrupt is generated (ICP(0 to 11) =1). *1: ICP(6, 7) of CY91F591/2/4/6/7/9 are used for LSYN only. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 918: Edge Detection Specifications For Input Capture And Their Operations
When falling edge is selected (4) Falling edge of the input signal is detected. (5) Free-run counter value is recorded to the capture register (capture). (6) Input capture interrupt is generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 919 (11) Falling edge of the input signal is detected. (12) Free-run counter value is recorded to the capture register (capture). (13) Input capture interrupt is generated. *1: ch.6 and 7 of CY91F591/2/4/6/7/9 are used for LSYN only. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 920: Setting
(ICS01), (ICS23), (ICS45), (ICS67) , (ICS89), (ICS1011) Interrupt request enable *1: ch.6 and 7 of CY91F591/2/4/6/7/9 are used for LSYN only. *2: ch.8 to 11 are only supported by CY91F59A/B. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 921: Q&A
23.7.2 How to Enable External Input Pins (ICU0 to ICU11) 23.7.3 About Interrupt Related Registers 23.7.4 About Interrupt Types 23.7.5 How to Enable Interrupt 23.7.6 How to Measure the Pulse Width of the Input Signal CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 922: Effective Edge Polarity Of External Input: Types And How To Select
Effective edge polarity bits of the external input (EG[01:00]), (EG[11:10]), (EG[21:20]), (EG[31:30]), (EG[41:40]), (EG[51:50]), Operation (EG[61:60]), (EG[71:70]), (EG[81:80]),(EG[91:90]), (EG[101:100]),(EG[111:110]) To select rising edge Select "01". To select falling edge Select "10". To select both edges Select "11". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 923: How To Enable External Input Pins (Icu0 To Icu11)
Also, set the ICU0 to ICU11 pins for peripheral input. For information on the setting method, see "Chapter: I/O Ports". *1: ch.6 and 7 of CY91F591/2/4/6/7/9 are used for LSYN only. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 924: About Interrupt Related Registers
Therefore, clear the input capture interrupt request flags (ICP0, ICP1, ICP2, ICP3, ICP4, ICP5, ICP6, ICP7, ICP8, ICP9, ICP10, ICP11) by writing "0" using software before returning from interrupt processing. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 925: About Interrupt Types
Input Capture 23.7.4 About Interrupt Types This section explains interrupt types. There is only 1 type of interrupt. It is generated when an edge is detected in the input signal. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 926: How To Enable Interrupt
(ICS01:ICP0), (ICS01:ICP1), (ICS23:ICP2), (ICS23:ICP3), (ICS45:ICP4), (ICS45:ICP5), (ICS67:ICP6), (ICS67:ICP7), (ICS89:ICP8), (ICS89:ICP9), (ICS1011:ICP10), (ICS1011:ICP11) Interrupt request flag bits Operation (ICP0), (ICP1), (ICP2), (ICP3), (ICP4), (ICP5), (ICP6), (ICP7), (ICP8), (ICP9), (ICP10), (ICP11) Interrupt request clear Write "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 927: How To Measure The Pulse Width Of The Input Signal
- {1st recorded value (input capture register value) × Count clock width of the free-run timer Note. This calculation formula is an example that is not use compare match clear function. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 928: Sample Program
-Vector table setting #pragma intvect INPUT0_int 52 (Note) Clock-related settings and the setting of __set_il (numeric value) need to be configured in advance. See “Chapter: Clock” and “Chapter: Interrupts Control (Interrupts Controller)”. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 929: Notes
Reading of the input capture register must be performed in word(32-bit mode) access. Read-modify-write The input capture interrupt request bits (ICP0), (ICP1), (ICP2), (ICP3), (ICP4), (ICP5), (ICP6), (ICP7), (ICP8), (ICP9), (ICP10), and (ICP11) are "1" when read using a read-modify-write (RMW) instruction. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 930: Real-Time Clock(Rtc)
24. Real-Time Clock(RTC) This chapter explains the real-time clock (RTC). 24.1 Overview 24.2 Features 24.3 Configuration 24.4 Registers 24.5 Operation 24.6 Setting 24.7 Q&A 24.8 Sample Program 24.9 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 931: Overview
The real-time clock operates as the real-world timer and provides the real-world timer information. Figure 24-1. Block Diagram (Overview) RTC clock Interrupt Sub-second register Second Minute Hour 0.5 Second Counter Sub-second counter Counter divider WOT External pin CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 932: Features
Interrupts can be generated based on five intervals: 0.5second, 1second, 1minute, 1hour, and 1day. In addition, interrupts at any interval (from short interval to long interval) can be generated by changing the sub-second value. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 933: Configuration
Real-Time Clock(RTC) 24.3 Configuration This section explains the configuration of the real-time clock (RTC). Figure 24-2. Configuration Diagram INTE2 CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 934: Registers
Register function Day/Hour/Minute/Second 0x055C Reserved Reserved WTDR Registers(day) 0x0560 Reserved WTCR RTC control register 0x0564 Reserved WTBR Sub-second register Day/Hour/Minute/Second registers(hour) Day/Hour/Minute/Second 0x0568 WTHR WTMR WTSR Reserved registers(minute) Day/Hour/Minute/Second registers(second) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 935: Rtc Control Register : Wtcr
The read value is always "1". The data writing does not affect the operation. [bit17] INTE4 : 0.5 second interrupt request enable INTE4 Operation 0.5 second interrupt request disabled 0.5 second interrupt request enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 936 1 hour interrupt request not generated Flag clear 1 hour interrupt request generated This does not affect the operations When overflow occurs in the minute counter, the flag will be set to "1". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 937 When overflow occurs in the 0.5 second counter, the flag will be set to "1". [bit7 to bit4] Reserved These bits must always be written to "0". [bit3] RUN : Operation state State Real-time clock module is stopped Real-time clock module is running CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 938 To write "1" to the update bit (UPDT), do it while RTC is working (ST=1). Note: While the update bit (UPDT) is "1", writing "0" to the start bit (ST) (RTC stop) is prohibited. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 939: Sub-Second Register : Wtbr
The sub-second register settings for counting 0.5 second are as follows: Table 24-2. WTBR Setting Example RTC clock frequency WTBR Setting value 32kHz 0x001F3F 4MHz 0x0F423F CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 940: Day/Hour/Minute/Second Register : Wtdr/ Wthr/ Wtmr/ Wtsr
Attribute WTHR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value Attribute R1,WX R1,WX R1,WX WTMR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value Attribute R1,WX R1,WX CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 941 As this series does not provide the RTC detection reset function, the Day/Hour/Minute/Second registers are cleared only in case of power-on reset. Therefore, when the microcomputer internal low voltage detection flag is set, the Day/Hour/Minute/Second registers are recommended to be cleared. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 942: Operation
Figure 24-4. Operation Descriptions for the Real-time Clock (1) Use the start bit (ST="0") to reset the sub-second counter (22-bit down counter) and Day/ Hour/ Minute/ Second timers (0), and then stop them. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 943 (16) Set the start bit (ST) to "0". (17) Use the start bit ST="0" to clear(reset) the sub-second counter (22-bit down counter) and the Day/ Hour/ Minute/ Second counters, and then stop them. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 944: Setting
Setting of the RTC interrupt vector and the RTC interrupt See "Chapter: Interrupt Control (Interrupt Controller)". 24.7.10 level RTC interrupt setting Interrupt request clear RTC Control Register (WTCR) 24.7.11 Interrupt request enable CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 945: Q&A
How to Stop the Real-time Clock? 24.7.8 How to Calibrate the Real-time Clock? 24.7.9 What Are Interrupt Related Registers? 24.7.10 What Are the Interrupt Types and How to Select Them? 24.7.11 How to Enable Interrupts? CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 946: How To Set The 0.5 Second Count Interval
This section explains how to set the 0.5 second count interval. Stop the real-time clock, and set the value indicated in Table 24-2. WTBR Setting Example to the sub-second register(WTBR) according to the RTC clock frequency. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 947: How To Initialize The Real-Time Clock
Write "0" instead of "1" to the start bit to reset all the bits of the Hour/ Minute/ Second counters and the subsecond counter (22-bit down counter) to "0" (initialization) and to stop counting. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 948: How To Set/Update Number Of Days (Day) And Time (Hour/Minute/Second)
Write the values in Day/ Hour/ Minute/ Second registers(WTDR, WTHR, WTMR, WTSR), and then update them using the update bit (UPDT). Operation Update bit (UPDT) To update the Day/ Hour/ Minute/ Second counters Set to "1" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 949: How To Start/Stop The Count Of The Real-Time Clock
Use the start bit (WTCR:ST) to set. Operation Start bit (ST) To stop the count of the real-time clock Set to "0" To start the count of the real-time clock Set to "1" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 950: How To Confirm That The Real-Time Clock Is Running
This section explains how to confirm that the real-time clock is running. Confirm using the operation flag (WTCR:RUN). Operation Operation flag (RUN) The real-time clock has stopped "0" can be read The real-time clock is running "1" can be read CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 951: How To Know The Number Of Days And Time
When read from hour: 1 day 2 hours 59 minutes 59 seconds => 1 day 2 hours 0 minute 0 second => 1 day 3 hours 0 minute 0 second CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 952: How To Stop The Real-Time Clock
Real-Time Clock(RTC) 24.7.7 How to Stop the Real-time Clock? This section explains how to stop the real-time clock. "24.7.4 How to Start/Stop the Count of the Real-time Clock?". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 953: How To Calibrate The Real-Time Clock
This section explains how to calibrate the real-time clock. When the sub clock(only dual clock product) is selected as the RTC clock, the ratio of main clock: sub clock can be used for calibration. See "Chapter: RTC/WDT1 Calibration". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 954: What Are Interrupt Related Registers
The interrupt request flags (INT0, INT1, INT2, INT3, INT4) are not automatically cleared. Therefore, use software to clear the flags prior to restoration from interrupt processing. (Write "0" to INT0, INT1, INT2, INT3, INT4 bits) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 955: What Are The Interrupt Types And How To Select Them
INT2 INTE2 1 day count timing INT3 INTE3 Time(0.5 second) count timing INT4 INTE4 As interrupt occurs by OR of these five factors, select using the interrupt request enable bit. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 956: How To Enable Interrupts
Use the interrupt request bits (WTCR:INT0, WTCR:INT1, WTCR:INT2, WTCR:INT3, WTCR:INT4) to clear interrupt requests. Setting procedure Operation Interrupt request bits (INT0, INT1, INT2, INT3, INT4) To clear interrupt requests Write "0" CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 957: Sample Program
Setting of the vector table <Other> (Note) Clock related settings and __set_il (number) setting are required to be performed in advance. See “Chapter: Clock” and ‘Chapter: Interrupt Control (Interrupt Controller)”. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 958: Notes
RTC is not initialized. If the reset input from the RSTX pin input or the external low-voltage detection flag is set after the start-up, initialize the register of RTC before using. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 959 Real-Time Clock(RTC) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 960: Rtc/Wdt1 Calibration
25. RTC/WDT1 Calibration This chapter explains the RTC/WDT1 calibration. 25.1 Overview 25.2 Features 25.3 Configuration 25.4 Registers 25.5 Operation CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 961: Overview
25.1 Overview This section explains the overview of the RTC/WDT1 calibration. This module calculates the values for frequency calibrations in CR oscillation circuit built in real-time clock, WDT1 and CSV. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 962: Features
CR clock frequency from the main clock frequency to set the CR clock trimming value. Figure 25-1. Comparison for Counters Driven by Different Clocks Sub clock/ CR oscillation clock Sub/CR counter CUTD CUTD-1 Main oscillation New CUTR Old CUTR counter Comparison in progress CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 963: Configuration
Bus access Main clock Calibration unit 0 (for RTC) Sub clock (Only dual clock product) Calibration unit 1 (for WDT) CRTR TRD[7:0] To CSV CR oscillation circuit CR oscillation clock CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 964: Registers
Calibration unit control register 1 0x04C4 CUCR1 CUTD1 CR oscillation timer data register 0x04C8 CUTR1 Main oscillation timer data register 1 0x04CC CRTR Reserved Reserved Reserved CR oscillation trimming setting register CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 965: Calibration Unit Control Register 0 : Cucr0 (Calibration Unit Control Register 0)
"0". [bit0] INTEN (calibration INTerrupt ENable) : Interrupt enable This bit sets whether to generate an interrupt when the INT bit is set. INTEN Interrupt Disabled Enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 966: Sub Clock Timer Data Register : Cutd0 (Calibration Unit Timer Data Register 0)
TDD[7:0] Initial value Attribute [bit15 to bit0] TDD[15:0] (Timer Data Data field) : Timer data These bits configure the comparison time interval in number of sub clocks. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 967: Main Oscillation Timer Result Register 0 : Cutr0 (Calibration Unit Timer Result Register 0)
These bits display the value of the count in the comparison interval. Read the results at the end of comparison results. The read value during comparison is undefined. Writing has no effect on operation. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 968: Calibration Unit Control Register 1 : Cucr1 (Calibration Unit Control Register 1)
"0". [bit0] INTEN (calibration INTerrupt Enable) : Interrupt enable This bit sets whether to generate an interrupt when the INT bit is set. INTEN Interrupt Disabled Enabled CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 969: Cr Clock Timer Data Register : Cutd1 (Calibration Unit Timer Data Register 1)
TDD[7:0] Initial value Attribute [bit15 to bit0] TDD[15:0] (Timer Data Data field) : Timer data These bits configure the comparison time interval in number of CR clocks. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 970: Main Oscillation Timer Result Register 1 : Cutr1 (Calibration Unit Timer Result Register 1)
These bits display the value of the count in the comparison interval. Read the results at the end of comparison. The read value during comparison is undefined. Writing is disabled. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 971: Cr Oscillation Trimming Setting Register : Crtr (Cr Oscillator Calibration Trimming Register)
-47.61% -47.23% 0% (Initial value) +45.62% +45.98% +46.37% *: As changes take place according to conditions such as temperature, it is necessary to perform using the procedure explained at "5.2". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 972: Operation
RTC/WDT1 Calibration 25.5 Operation This section explains an operation of the RTC/WDT1 calibration. 25.5.1 Real-Time Clock (RTC) Calibration 25.5.2 WDT1 Calibration (CR Clock Calibration) 25.5.3 Notes CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 973: Real-Time Clock (Rtc) Calibration
Comparison of CUTR0 and CUTD0 can be used to calculate the ratio of the main clock frequency and the frequency of sub clock. Sets the prescaler value in RTC using the value calculated at (7). CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 974: Wdt1 Calibration (Cr Clock Calibration)
Substitute 0 to 255 for n in the following formula, and find n which makes Fer the minimum, which is the trimming value. Fstep = (Fmax - Fmin) / 255 Fer = | (100kHz) - (Fmin + Fstep × n) | CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 975: Notes
"1" again to redo. > 2 × TOSC4 + 3 × TCLKP should be satisfied. OSC32/OSC100 TOSC4: Main clock period TOSC32: Sub clock period TOSC100: CR oscillator period TCLK: Peripheral clock period CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 976: Power Consumption Control
26. Power Consumption Control This chapter explains the power consumption control. 26.1 Overview 26.2 Features 26.3 Configuration 26.4 Registers 26.5 Operation 26.6 Example of Use CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 977: Overview
26.1 Overview This section explains the overview of the power consumption control. This series have variety of low-power consumption modes and can perform the power consumption control feature accordingly for situations. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 978: Features
Power-shutdown of GDC unit By setting this mode, GDC unit can be controlled to power-shutdown state separately from microcontroller unit. Unless setting GDC unit to power-shutdown, microcontroller unit cannot go into standby mode. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 979: Configuration
Signal (Microcontroller → Always ON) Regulator 0 5V Power Microcontroller supply Signal(GDC → Power Switch control Microcontroller) Regulator 1 3V Power supply Regulator 2 Shut-down IO shut-down FR81S Oscillation IO OSCD CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 980 CPU sleep request Bus sleep request SLEEP STBCR read SLVL[1] TIMER Clock stop request STBCR read Bus acknowledge STOP STBCR read Oscillator stop request Return Reset factor STBCR : Standby control register CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 981: Registers
Internal low-voltage detection Simultaneous assert of RSTX and NMIX external pins Hardware watchdog reset * : Registers are not initialized by reset of the INIT level and RST level. (exception for STBCR) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 982: Standby Control Register : Stbcr (Standby Mode Control Register)
The read value is always "0". This bit must always be written to "0". [bit3, bit2] Reserved The read value is always "0". These bits must always be written to "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 983 Bus sleep mode (stop CPU and on-chip bus) * * : On-chip bus will run when DMA transfer is in progress. For information on pins with high impedance, see "Appendix". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 984: Pmu Control Register : Pmuctlr (Power Management Unit Control Register)
The read value is always "0". These bits must always be written to "0". 26.4.3 Power on Timing Control Register : PWRTMCTL (PoWeR on TiMing ConTroL register) The bit configurations of the Power on Timing control register are shown below. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 985: Power On Timing Control Register : Pwrtmctl (Power On Timing Control Register)
These bits set the rising time for PSW. Remarks of the case that PTC[2:0] Rising time PMUCLK=32kHz 30μS 1×(1/PMUCLK) 90μS 3×(1/PMUCLK) 150μS 5×(1/PMUCLK) 270μS 9×(1/PMUCLK) Prohibit 60μS 2×(1/PMUCLK) 120μS 4×(1/PMUCLK) 210μS 7×(1/PMUCLK) CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 986: Pmu Interrupt Flag Register 0 : Pmuintf0 (Power Management Unit Interrupt Flag0 Register)
-> The number from 15 to 8 is assigned. These bits are enabled only at shutdown. These bits are cleared by writing to "0". Writing to "1" is invalid. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 987: Pmu Interrupt Flag Register 1 : Pmuintf1 (Power Management Unit Interrupt Flag1 Register)
-> The number from 7 to 0 is assigned. These bits are enabled only at shutdown. These bits are cleared by writing to "0". Writing to "1" is invalid. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 988: Pmu Interrupt Flag Register 2 : Pmuintf2 (Power Management Unit Interrupt Flag2 Register)
This bit is cleared by writing to "0". Writing to "1" is invalid. MTIF is not set during return from the standby mode (shut-down) because the internal reset is generated. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 989 STIF is not set during return from the standby mode (shut-down) because the internal reset is generated. [bit3 to bit0] Reserved The read value is always "0". These bits must always be written to "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 990: Gdc Status Register : Gstr (Gdc Status Register)
This bit indicates the status of power supply in GDC. GPWRST State of power supply power off or instability of GDC regulator during power-on [bit6 to bit0] Reserved The read value is always "0". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 991: Gdc Control Register : Gctlr (Gdc Control Register)
[bit0] GPD (Gdc Power Down) This bit controls PD of regulator in GDC. PD control Disabled (GDC regulator ON) Enabled (GDC regulator OFF) * This bit is not initialized by a hardware watchdog. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 992: Operation
26.5.7 Standby Mode : Stop Mode with power-shutdown 26.5.8 Stop State of Microcontroller 26.5.9 Power-shutdown GDC Unit 26.5.10 Transition to Illegal Standby Mode 26.5.11 GDC Regulator 26.5.12 Restrictions on Power Shutdown and Normal Standby Control CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 993: Clock Control
Following clocks have the setting to stop separately.  External bus clock (TCLK): Can select to supply/stop in bus sleep mode For details on the setting method, see "Chapter: Clock". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 994: List Of Clock Supply In Low-Power Consumption Mode
*3: During sleep mode, the CR oscillation does not stop, but the watchdog timer 1 (HWWDT) stops. *4: It is necessary to set it beforehand to stop the CR oscillation at the standby. See the description of CSVCR:RCE in "Chapter: Clock Supervisor". CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 995: Sleep Mode
In FR81S core, if the read value will not be used in the next instruction, that instruction is executed before the read is completed. Perform dummy processing to use the read value in the next instruction so as not to make the program progress before entering sleep mode. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 996 This mode does not decrease power consumption as much as that of in watch mode or stop mode because the peripheral clock (PCLK) will continue to run. While, a return to the program operation within several clock times is possible by generating a wake up request. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 997: Standby Mode : Watch Mode
TIMER bit ="1", SLVL setting #_STBCR, R12 R0, @R12 Write LDUB @R12, R0 Read (activation of watch mode) R0, R0 Dummy processing for pipeline adjustment Dummy processing for pipeline adjustment CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 998 * : When continue to run program with activate clocks. CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 999: Standby Mode : Watch Mode With Power-Shutdown
TIMER bit ="1", SLVL setting #_STBCR, R12 R0, @R12 Write LDUB @R12, R0 Read (activation of watch mode with power-shutdown) R0, R0 Dummy processing for pipeline adjustment Dummy processing for pipeline adjustment CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...
Page 1000 Flash OFF control Microcontroller Microcontroller OFF control マイコン OFF制御マイコン OFF制御 OFF control Isolation valid Isolation有効 Watch (Clock, Reset 時計(ShutDown) (クロック、リセット) (ShutDown) PSW ON (Weak, Strong) PSW OFF (Weak、Strong) Return 戻る CY91590 Series FR81S Hardware Manual, Document Number: 002-05526 Rev. *B...

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