DEBIX Infinity User Manual page 23

The MIPI CSI interface is defined as follows:
Table 8 Pin definition of MIPI CSI
Pin Definition
1 SW_VDD5V
2 VDD_3V3
3 VDD_1V8
4 CSI1_PWDN
5 CSI1_nRST
6 I2C2_SDA
7 I2C2_SCL
8 CSI1_SYNC
9 CSI1_MCLK
10 GND
11 CSI1_DN0
12 CSI1_DP0
13 GND
14 CSI1_DN1
15 CSI1_DP1
16 GND
17 CSI1_CKN
18 CSI1_CKP
19 GND
20 CSI1_DN2
21 CSI1_DP2
22 GND
23 CSI1_DN3
24 CSI1_DP3
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Description
5V output
3.3V output
1.8V output
CSI low power mode
CSI reset signal
I2C data signal
I2C clock signal
CSI synchronization signal
CSI external clock input
To Ground
CSI Differential data channel 0 (-)
CSI Differential data channel 0 (+)
To Ground
CSI Differential data channel 1 (-)
CSI Differential data channel 1 (+)
To Ground
CSI Differential Clock Channels (-)
CSI Differential Clock Channels (+)
To Ground
CSI Differential data channel 2 (-)
CSI Differential data channel 2 (+)
To Ground
CSI Differential data channel 3 (-)
CSI Differential data channel 3 (+)
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