Csv Diagram And Relationship Of Monitored Clock And Reference Clock - Infineon XMC7000 Manual

Clock configuration setup in XMC7000 MCU family
Supplementary information
6.3

CSV diagram and relationship of monitored clock and reference clock

Figure 42 shows the clock diagram with monitored clock and reference clock for CSV.
relationship between monitored clock and reference clock.
IMO
EXT_CLK
ECO
ECO
Prescaler
Active Domain
ILO0
ILO1
WCO
LEGEND 1:
Relationship of Monitored Clock and Reference Clock
Monitored Clock
Reference Clock
Figure 42 CSV diagram
Application note
FLL
PATH_MUX0
DSI_MUX0
PLL400
#0
PATH_MUX1
DSI_MUX1
PLL400
#1
PATH_MUX2
DSI_MUX2
PLL200
#0
PATH_MUX3
DSI_MUX3
PLL200
#1
PATH_MUX4
DSI_MUX4
PATH_MUX5
DSI_MUX5
CLK_REF_HF
REF_MUX
CLK_ILO0
LFCLK_SEL
CLK_BAK
CLK_SEL
Active Domain
Reset /
CSV
Fault Reporting
CLK_PATH0
Predivider
(1/2/4/8)
BYPASS_MUX0
ROOT_MUX0
CLK_PATH1
Predivider
(1/2/4/8)
BYPASS_MUX1
ROOT_MUX1
Predivider
CLK_PATH2
(1/2/4/8)
ROOT_MUX2
BYPASS_MUX2
Predivider
(1/2/4/8)
CLK_PATH3
ROOT_MUX3
BYPASS_MUX3
Predivider
(1/2/4/8)
CLK_PATH4
ROOT_MUX4
BYPASS_MUX4 Predivider
(1/2/4/8)
ROOT_MUX5
CLK_PATH5
Predivider
(1/2/4/8)
ROOT_MUX6
Predivider
(1/2/4/8)
ROOT_MUX7
CSV_ILO
CSV_LF
CLK_LF
DeepSleep Domain
Hibernate Domain
DeepSleep Domain
Monitored Clock
Reference Clock
37
Table 4 shows the
CSV_HF0
CLK_HF0
CSV_HF1
CLK_HF1
CSV_HF2
CLK_HF2
CSV_HF3
CLK_HF3
CSV_HF4
CLK_HF4
CSV_HF5
CLK_HF5
CSV_HF6
CLK_HF6
CSV_HF7
CLK_HF7
CSV_REF
Wakeup
CSV
Fault Reporting
002-34253 Rev. *C
2023-11-08