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Clock configuration setup in XMC7000 MCU family
Internal clock configuration
5.4
Configuring CLK_FAST_0/CLK_FAST_1
CLK_FAST_0 and CLK_FAST_1 are generated by dividing CLK_HF1 by (x+1). When configuring CLK_FAST_0 and
CLK_FAST_1, configure a value (x = 0..255) divided by the FRAC_DIV bit and INT_DIV bit of the
CPUSS_FAST_0_CLOCK_CTL register and CPUSS_FAST_1_CLOCK_CTL register.
5.5
Configuring CLK_MEM
CLK_MEM is generated by dividing CLK_HF0; its frequency is configured by the value obtained by dividing
CLK_HF0 by (x+1). When configuring CLK_MEM, configure a value (x = 0..255) divided by the INT_DIV bit of the
CPUSS_MEM_CLOCK_CTL register.
5.6
Configuring CLK_PERI
CLK_PERI is the clock input to the peripheral clock divider and CLK_GR. CLK_PERI is generated by dividing
CLK_HF0; its frequency is configured by the value obtained by dividing CLK_HF0 by (x+1). When configuring
CLK_PERI, configure a value (x = 0..255) divided by the INT_DIV bit of the CPUSS_PERI_CLOCK_CTL register.
5.7
Configuring CLK_SLOW
CLK_SLOW is generated by dividing CLK_MEM; its frequency is configured by the value obtained by dividing
CLK_MEM by (x+1). After configuring CLK_MEM, configure a value divided (x = 0..255) by the INT_DIV bit of the
CPUSS_SLOW_CLOCK_CTL register.
5.8
Configuring CLK_GR
The clock source of CLK_GP is CLK_PERI in Group 3, 4, 8, and CLK_HF2 in Group 5, 6, and 9. Groups 3, 4, and 8
are clocks divided by CLK_PERI. To generate CLK_GR3, CLK_GR4, and CLK_GR8, write the division value (from 1
to 255) to divide the INT8_DIV bit of the CPUSS_PERI_GRx_CLOCK_CTL register.
5.9
Configuring PCLK
PCLK is a clock that activates each peripheral function. Peripheral Clock Dividers have a function to divide
CLK_PERI and generate a clock to be supplied to each peripheral function. For assignment of the peripheral
clocks, see the "Peripheral Clocks" section in the datasheet.
Figure 34
shows the flow to set peripheral clock dividers. See the
manual
for more details.
Application note
XMC7000 MCU family architecture reference
28
002-34253 Rev. *C
2023-11-08
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