Code Preview; Configuring Clk_Lf - Infineon XMC7000 Manual

Clock configuration setup in XMC7000 MCU family
Internal clock configuration
5.2.1

Code preview

Figure 32 Code preview for CLK_HFx configuration
5.3

Configuring CLK_LF

CLK_LF can be selected from one of the possible sources: WCO, ILO0, ILO1, and ECO_Prescaler. CLK_LF cannot
be set when the WDT_LOCK bit in the WDT_CTL register is disabled because CLK_LF can select ILO0 that is input
clock for the WDT.
Figure 33 shows the details of LFCLK_SEL that CLK_LF is configured.
Figure 33 LFCLK_SEL
Table 1 shows the required registers for CLK_LF. See the
for more details.
Table 1 Configuring of CLK_LF
Register name
CLK_SELECT
Application note
ILO0
ILO1
WCO
ECO_Rrescaler
Bit name
LFCLK_SEL[2:0]
CLK_LF
LFCLK_SEL
XMC7000 MCU family architecture reference manual
Value
0
1
5
6
Other
27
Selected item
ILO0
WCO
ILO1
ECO_Prescaler
Reserved. Do not use.
002-34253 Rev. *C
2023-11-08