Clock System Functions - Infineon XMC7000 Manual

Clock configuration setup in XMC7000 MCU family
Clock system for XMC7000 family MCUs
2.3

Clock system functions

Figure 2 shows the details of the clock selection and multiplier block. This block generates root frequency
clocks CLK_HF0 to CLK_HF7 from the clock resources. This block has the capability to select one of the
supported clock resources – FLL and PLL to generate the required high-speed clock. This MCU supports two
types of PLLs: PLL without spread spectrum clock generation (SSCG) and fractional operation (PLL200#x), and
PLL with SSCG and fractional operation (PLL400#x).
IMO
EXT_CLK
ECO
ECO
Prescaler
Active Domain
ILO0
ILO1
WCO
Figure 2 Clock system block diagram
Application note
FLL
BYPASS_MUX0
PATH_MUX0
DSI_MUX0
PLL400
#0
BYPASS_MUX1
PATH_MUX1
DSI_MUX1
PLL400
#1
BYPASS_MUX2
PATH_MUX2
DSI_MUX2
PLL200
#0
BYPASS_MUX3
PATH_MUX3
DSI_MUX3
PLL200
#1
BYPASS_MUX4
PATH_MUX4
DSI_MUX4
PATH_MUX5
DSI_MUX5
CLK_REF_HF
REF_MUX
CLK_ILO0
LFCLK_SEL
CLK_BAK
CLK_SEL
6
CLK_PATH0
Predivider
(1/2/4/8)
ROOT_MUX0
CLK_PATH1
Predivider
(1/2/4/8)
ROOT_MUX1
Predivider
CLK_PATH2
(1/2/4/8)
ROOT_MUX2
Predivider
(1/2/4/8)
CLK_PATH3
ROOT_MUX3
Predivider
(1/2/4/8)
CLK_PATH4
ROOT_MUX4
Predivider
(1/2/4/8)
ROOT_MUX5
CLK_PATH5
Predivider
(1/2/4/8)
ROOT_MUX6
Predivider
(1/2/4/8)
ROOT_MUX7
CSV
CSV
CLK_LF
DeepSleep Domain
Hibernate Domain
CSV
CLK_HF0
CSV
CLK_HF1
CSV
CLK_HF2
CSV
CLK_HF3
CSV
CLK_HF4
CSV
CLK_HF5
CSV
CLK_HF6
CSV
CLK_HF7
CSV
002-34253 Rev. *C
2023-11-08