Pclk Configuration Example; Use Case - Infineon XMC7000 Manual

Clock configuration setup in XMC7000 MCU family
Internal clock configuration
5.9.1

PCLK configuration example

5.9.1.1

Use case

Parameter
Input clock frequency
Output clock frequency
Divider type
Used divider
Peripheral clock output number
Define PCLK_TCPWMx_CLOCKSx_COUNTER,
Define TCPWM_PERI_CLK_DIVIDER_NO_COUNTER
(1)
Set Input/Output Frequency and Divide Number
(2)
(3)
(4)
Figure 35 Example procedure for setting PCLK
Application note
Start
Assign divider to peripheral
Configure the Clock Divider 16.0#0
Enable Clock Divider 16.0#0
End
Value
80 MHz
2 MHz
Clock divider 16.0
Clock divider 16.0#0
31 (TCPWM0, Group#0, Counter#0)
Divide Number = Input Freq/Output Freq
Clock Divider 16.0#0 assign to
TCPWM0 Group#0 Channel#0
30 002-34253 Rev. *C
2023-11-08