Configuring Clk_Hfx - Infineon XMC7000 Manual

Clock configuration setup in XMC7000 MCU family
Internal clock configuration
5.2

Configuring CLK_HFx

CLK_HFx (x=0,1,2,3,4,5,6,7) can be selected from any CLK_PATHy (y=0,1,2,3,4,5). A predivider is available to
divide the selected CLK_PATHx. CLK_HF0 is always enabled because it is the source clock for the CPU cores.
CLK_HFx can be disabled.
To enable CLK_HFx, write '1' to the ENABLE bit of each CLK_ROOT_SELECT register. To disable CLK_HFx, write
'0' to the ENABLE bit of each CLK_ROOT_SELECT register.
The ROOT_DIV bit of the CLK_ROOT register sets the predivider values from the options: No division, divide by
2, by 4, and by 8.
Figure 30 shows the details of ROOT_MUX and the predivider.
0
CLK_PATH0
CLK_PATH1
CLK_PATH2
CLK_PATH3
CLK_PATH4
CLK_PATH5
Figure 30 ROOT_MUX and predivider
You can configure CLK_HFx in the System tab of the Device Configurator. ModusToolbox™ software
automatically generates the corresponding code.
Figure 31 CLK_HFx configuration
Application note
Predivider
ROOT_DIV
ROOT_MUX
26
CLK_HF0 / CLK_HF1 / CLK_HF2 / CLK_HF3 /
CLK_HF4 / CLK_HF5 / CLK_HF6 / CLK_HF7
002-34253 Rev. *C
2023-11-08