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Clock configuration setup in XMC7000 MCU family
FLL and PLL configuration
Select FLL, and in the FLL – Parameters pane, under General, enter the Desired Frequency (MHz) as 100.000 to
set the frequency as 100 MHz.
Figure 18 Setting output clock frequency as 100.000 MHz
4.1.3

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Figure 19 Code preview
Application note 19 002-34253 Rev. *C
2023-11-08