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(2) Access timing
Figure 3-50. Access Timing of 16-Bit Separated Asynchronous Bus
A14-00
in
During write operation
D15-00
During read operation
in/out
IOCS_B,
MCS_B
in
RD_B
in
WR_B
in
(Hi-Z)
RDY
out
If RD_B or WR_B is asserted when IOCS_B or MCS_B is asserted, RDY is immediately negated and the register
or memory at the address indicated by A[14:0] is accessed.
If RD_B is asserted, a read operation is started. When data output is ready, the data is output to D[15:0], and
RDY is asserted. When the microprocessor receives the data and negates IOCS_B and MCS_B, the µ PD98410
immediately makes RDY and D[15:0] go into a high-impedance state.
If WR_B is asserted, a write operation is started. When the data on D[31:0] is loaded and the operation in the
next bus cycle is enabled, RDY is asserted. When the microprocessor negates IOCS_B and MCS_B, the
µ PD98410 immediately makes RDY go into a high-impedance state.
Caution Do not assert RD_B and WR_B at the same time.
116
CHAPTER 3 FUNCTIONAL OUTLINE
Address
Valid
Read operation
Write operation
Valid
(Hi-Z)
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