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The µ PD98410 (NEASCOT-X10) is an LSI integrating ATM switch functions on a single chip. It has four UTOPIA
Level2 interfaces and can switch 24 × 24 circuits by connecting multiple PHY devices. This LSI employs a shared
buffer non-blocking type switch and realizes a switch capacity of 1.2G bps by using an externally connected SRAM
for buffering cells.
1.1 Features
• Conforms to ATM FORUM UNI Version 3.1 & 4.0
• Realizes all switch functions with a single chip
• Non-blocking type with switch capacity of 1.2G bps
• Can switch 24 logical ports via four UTOPIA Level2 (8 bits/40 MHz) interfaces
• Multi-speed (155M bps, 52M bps, 25M bps, etc.)
• Supports 16K/32K/64K VP/VC and 1K/2K/4K multi-cast VP/VC
• Shared buffer architecture using standard SRAM
• Cell buffer capacity: 12.8K/25.6K/51.2K cells
• Supports four QOS classes (CBR, VBR, ABR, UBR)
• ABR traffic control (binary mode)
• Supports EPD (Early Packet Discard) and PPD (Partial Packet Discard)
• +3.3-V single power source (directly connectable with +5-V TTL level signals)
• Test function: Supports JTAG (IEEE 1149.1)
1.2 Ordering Information
Part Number
µ PD98410S2-K6
CHAPTER 1 GENERAL
Package
580-pin plastic BGA (45 × 45 mm)
15
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