External Memory Interface; Htt & Control Memory Interface - NEC mPD98410 User Manual

3.12 External Memory Interface

3.12.1 HTT & control memory interface
A memory with 1 word being 36 bits wide (32 bits + 4-bit parity) and a depth of 64K words is connected as the
HTT & control memory. This memory can be expanded along with the cell buffer, and 128K word and 256K word
memories can be connected. This memory stores the HTT (Header Translation Table) and cell addresses (idle
queue/output queue/multi-cast queue).
The µ PD98410 translates headers by using the HTT. It accesses the HTT for inputting cells, multi-cast re-
queuing, and outputting cells. The HTT must be created by the microprocessor in accordance with a predetermined
format.
Caution The microprocessor can always access the HTT even while the µ µ µ µ PD98410 is performing a
switching operation, but a wait signal of up to 16 system clocks is inserted, until access by the
microprocessor is enabled.
Because the microprocessor runs memory diagnostics as necessary after reset, the memory can be accessed.
After running the memory diagnostics, the HTT & control memory must be selected by setting the HC bit of the
MODE register to "1". While the switching operation is enabled, the microprocessor can access the external memory
only to access the header translation table (HTT). The control memory must not be accessed.
Figure 3-52. Example of Connecting HTT & Control Memory (minimum configuration)
118
CHAPTER 3 FUNCTIONAL OUTLINE
A[15:0]
WE_B
OE_B
D[15:0]
D[17:16]
CS_B
µ
PD98410
A[15:0]
WE_B
OE_B
D[15:0]
D[17:16]
CS_B