Polling During Cell Input - NEC mPD98410 User Manual

3.2.3 Polling during cell input

(1) Basic operation
Cells are input to the µ PD98410 in the following sequence:
The µ PD98410 inquires whether a PHY device has cells.
<1>
<2> The PHY device returns a response to indicate whether the device has cells.
This sequence is performed for a PHY device mapped to a logical port by PHY, UPN, and EN of the port
configuration register. Figure 3-12 shows the relationship between the clock and polling control at this time.
Polling control at the input side has no relationship with the basic operation cycle (= 54 UTOPIA clocks) units.
Figure 3-12. Relationship between Polling Control and Basic Operation Cycle (during cell input)
Clock
PHY address
0
to be polled
(RXADDR)
Result
(RXCLAV)
Caution Never map a PHY device that is not connected to a logical port. Otherwise, the input side polls a
PHY device that does not exist, resulting in a hang up of the corresponding UTOPIA receive
interface port.
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CHAPTER 3 FUNCTIONAL OUTLINE
Figure 3-11. Basic Operation of Polling during Cell Input
Input side
0
PHY
1
PHY UP0
2
I-Poling Contorl
UP1
3
PHY
.
.
UP2
.
11
PHY
UP3
1 2 3
OK
or
NG
Inquiry to determine whether
device has cells
Response to indicate whether
device has cells
The PHY address mapped to a logical port is polled
(PHY address 2 is not polled because it is not mapped).