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3.1.1 Input port interface
The µ PD98410 has four UTOPIA interfaces and supports multiple PHY device connection allowing up to 24 input
ports. Up to 12 ports can be connected to each UTOPIA interface.
An input port is mapped to a logical input port number based on the PHY address and UTOPIA interface number,
in accordance with the contents of the port configuration register. The µ PD98410 performs its internal processing by
using this logical input port number.
Figure 3-1 shows an example of connecting multiple PHY devices to one UTOPIA interface.
Figure 3-1. Example of Connecting UTOPIA Receive Interface
Multi-PHY - 1ATM
155 Mbps
52 Mbps
25 Mbps
Of the 5 bits of a PHY address, the low-order 4 bits are connected to the µ PD98410. Pull up the
Remark
highest bit. The µ PD98410 outputs a PHY address of "0" through "11" for the purpose of polling.
The µ PD98410 does not have an RXCLK output. Supply UCLKn to the µ PD98410 as a UTOPIA clock.
40
CHAPTER 3 FUNCTIONAL OUTLINE
RXCLK
RXADDR [4:0]
RXCLAV
PHY
RXENB_B
RXDATA [7:0]
RXSOC
RXCLK
RXADDR [4:0]
RXCLAV
PHY
RXENB_B
RXDATA [7:0]
RXSOC
RXCLK
RXxADDR [4:
RXCLAV
PHY
RXENB_B
RXDATA [7:0]
RXSOC
.
.
.
UTOPIA
Level 2
OSC
µ
PD98410
UCLKn
[4]
RXADDRn [3:0]
[3:0]
RXCLAVn
RXENBn_B
RXDATAn [7:0]
RXSOCn
(n:0, 1, 2, 3)
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