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5.4 Operation Description
5.4.1 TAP controller
The TAP controller is a circuit having 16 states synchronized with changes of the JMS and JCK pins. Its operation
is specified by IEEE Standard 1149.1.
5.4.2 TAP controller state
Figure 5-2 shows the state transition of the TAP controller.
depending on the state of the JMS pin signal input at the rising edge of the clock input to the JCK pin. The
operations of the instruction register, boundary scan register, and bypass register change at the rising or falling edge
of the clock input to the JCK pin. (Refer to Figure 5-3).
(1) Test-Logic-Reset
H
L
(2) Run-Test/Idle
L
Remarks 1. "H" and "L" of the arrows indicating state transition in the above figure indicate the state of the JMS
pin at the rising edge of the clock input to the JCK pin.
2. Numbers in ( ) in the above figure correspond to the explanation below.
176
CHAPTER 5 JTAG BOUNDARY SCAN
Figure 5-2. State Transition of TAP Controller
H
(3) Select-DR-Scan
L
H
(5) Capture-DR
L
(6) Shift-DR
H
L
(7) Exit1-DR
L
(8) Pause-DR
H
L
L
(9) Exit2-DR
H
(10) Update-DR
H
L
The state of the TAP controller is determined
H
(4) Select-IR-Scan
L
H
(11) Capture-IR
L
(12) Shift-IR
H
H
(13) Exit1-IR
L
(14) Pause-IR
H
L
(15) Exit2-IR
H
(16) Update-IR
L
H
H
L
H
L
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