NEC mPD98410 Manuals

Manuals and User Guides for NEC mPD98410. We have 1 NEC mPD98410 manual available for free PDF download: User Manual

NEC mPD98410 User Manual

NEC mPD98410 User Manual (209 pages)

1.2G ATM SWITCH LSI

Brand: NEC | Category: Switch | Size: 0.8 MB

Table of Contents

Table of Contents
7
Chapter 1 General

15
- Features
  15
- Ordering Information
  15
- Example of System Configuration (Application)
  16
- Block Diagram
  17
- Pin Configuration
  18
Chapter 2 Pin Functions

19
- Pin Configuration (Bottom View)
  19
- Pin Layout
  21
- Pin Functions
  27
- Power Supply
  27
- UTOPIA Interface
  28
- Memory Interface Signals
  32
- Microprocessor Interface Signals
  34
- Jtag
  36
- Others
  36
- Recommended Connections of Unused Pins
  37
- Pin Status at Reset
  38
Chapter 3 Functional Outline

39
- UTOPIA Interfaces
  39
- Input Port Interface
  40
- Output Port Interface
  41
- Polling
  42
- Outline of Polling
  42
- Polling During Cell Output
  44
- Polling During Cell Input
  50
- Header Translation
  56
- HTT (Header Translation Table) Memory Map
  56
- General
  57
- Format of HTT
  60
- Accessing HTT
  63
- Flow of Header Translation
  68
- Accessing HTT with RM Cell
  72
- Queue Control
  75
- Single Cast
  75
- Multi-Cast
  76
- Congestion Control
  77
- Cell Discard by Class
  81
- EPD (Early Packet Discard) Control
  82
- PPD (Partial Packet Discard) Control
  84
- Minimum Queue Length
  85
- ABR Congestion Control
  88
- EFCI (Explicit Forward Congestion Indicator)
  88
- RM Cell CI/NI Marking (Resource Management Cell CI/NI Congestion Indication Marking)
  88
- RM Cell Merge (Resource Management Cell Merge)
  89
- WFQ (Weighted Fairness Queue)
  90
- General
  90
- Counters and Flags Used
  90
- Peak Rate Shaping Function
  93
- General
  93
- Details
  95
- Successive Transmission
  99
- Interrupt Request
  103
- Parity Error
  103
- Input Port Overrun
  103
- Queue Pointer Error
  103
- Cast Count Error
  104
- Cell Buffer Memory Shortage
  104
- Control Memory Shortage
  104
- HEC/CRC Error
  104
- Header Translation Error
  105
- Exceeding Buffer Threshold Value
  105
- Count over Detection
  105
- Monitoring
  106
- Monitor Register
  106
- Cell Discard Count Due to Exceeded Threshold Value
  106
- Cell Discard Count Due to Header Translation Error
  106
- Cell Discard Count Due to HEC Error or CRC Error
  107
- Cell Discard Count Due to Control/Cell Buffer Memory Shortage
  107
- Counting Number of Received Cells
  108
- Microprocessor Interface
  109
- I/O Mapping and Memory Mapping
  110
- 32-Bit Multiplexed Synchronous Bus (HSEL = Low)
  113
- 16-Bit Separated Asynchronous Bus (HSEL = High)
  115
- External Memory Interface
  118
- HTT & Control Memory Interface
  118
- Cell Buffer Interface
  119
Chapter 4 Internal Registers

123
Chapter 5 Jtag Boundary Scan

173
- Features
  173
- Internal Configuration of Boundary Scan Circuit
  174
- Instruction Register
  174
- TAP (Test Access Port) Controller
  174
- Bypass Register
  174
- Boundary Scan Register
  174
- Pin Function
  175
- JCK (JTAG Clock) Pin
  175
- JMS (JTAG Mode Select) Pin
  175
- JDI (JTAG Data Input) Pin
  175
- JDO (JTAG Data Output) Pin
  175
- JRST_B (JTAG Reset) Pin
  175
- Operation Description
  176
- TAP Controller
  176
- TAP Controller State
  176
- TAP Controller Operation
  181
- Initializing TAP Controller
  184
- Instruction Register
  184
- BYPASS Instruction
  185
- EXTEST Instruction
  185
- Boundary Scan Data Bit Definition
  185
Chapter 6 Limitations

187
- Limitations
  187
- Description of Limitations
  188
CHAPTER 7 FAQ (Frequently Asked Questions)

195

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