Part 2.4: Qspi Flash - Alinx KINTEX UltraScale FPGA AXKU042 User Manual

PL_DDR4_A11
PL_DDR4_A12
PL_DDR4_A13
PL_DDR4_BA0
PL_DDR4_BA1
PL_DDR4_BG0
PL_DDR4_WE_B
PL_DDR4_RAS_B
PL_DDR4_CAS_B
PL_DDR4_CKE
PL_DDR4_ACT_B
PL_DDR4_CLK_N
PL_DDR4_CLK_P
PL_DDR4_CS_B
PL_DDR4_OTD
PL_DDR4_PAR
PL_DDR4_RST

Part 2.4: QSPI Flash

The AXKU042 FPGA development board is equipped with two 128MBit
Quad-SPI FLASH, and the model is N25Q128A, which uses the 3.3V CMOS
voltage standard. Due to the non-volatile nature of QSPI FLASH, it can store
FPGA configuration Bin files and other user data files in use. The specific
models and related parameters of QSPI FLASH are shown in Table 4-1.
Position
U14
QSPI FLASH is connected to the dedicated pins of BANK0 of the FPGA
chip. The clock pin is connected to CCLK0 of BANK0, and other data signals
are connected to D00~D03 of BANK0 and FCS pins. Figure 4-2 shows the
hardware connection of QSPI Flash and FPGA Chip.
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KINTEX UltraScale+ FPGA Board AXKU042 User Manual
IO_L24N_T3U_N11_45
IO_L14P_T2L_N2_GC_45
IO_L10N_T1U_N7_QBC_AD4N_45
IO_L18P_T2U_N10_AD2P_45
IO_L10P_T1U_N6_QBC_AD4P_45
IO_L16P_T2U_N6_QBC_AD3P_45
IO_L9N_T1L_N5_AD12N_45
IO_L8N_T1L_N3_AD5N_45
IO_L8P_T1L_N2_AD5P_45
IO_L14N_T2L_N3_GC_45
IO_L21N_T3L_N5_AD8N_45
IO_L22N_T3U_N7_DBC_AD0N_45
IO_L22P_T3U_N6_DBC_AD0P_45
IO_L21P_T3L_N4_AD8P_45
IO_L17P_T2U_N8_AD10P_45
IO_L20N_T3L_N3_AD1N_45
IO_L15N_T2L_N5_AD11N_45
Model
N25Q128A
Table 4-1: QSPI FLASH Specification
Amazon Store: https://www.amazon.com/alinx
Capacity
128M Bit
AD15
AH16
AL17
AG15
AL18
AJ15
AL15
AM19
AL19
AJ16
AF18
AE15
AE16
AE18
AG19
AF14
AG16
Factory
Numonyx