Atmel AT91FR40162S Manual
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Atmel AT91FR40162S Manual

Atmel AT91FR40162S Manual

At91 arm thumb microcontrollers
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Features

•
Incorporates the ARM7TDMI
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
™
– EmbeddedICE
(In-circuit Emulation)
•
256K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
•
1024K Words 16-bit Flash Memory (2M bytes)
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
•
Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
•
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
•
32 Programmable I/O Lines
•
3-channel 16-bit Timer/Counter
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
•
2 USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
•
Programmable Watchdog Timer
•
Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
•
Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85° C
•
2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
•
-40° C to 85° C Temperature Range
•
Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch

1. Description

The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR40162S ARM microcontroller features 2 Mbits of on-chip SRAM and 2
Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of
integration and very small footprint make the device ideal for space-constrained appli-
cations. The high-speed on-chip SRAM enables a performance of up to 74 MIPs in
typical conditions with significant power reduction and EMC improvement over an
external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-
programmed Flash Memory Uploader (FMU) using a single device supply, making the
AT91FR40162S suitable for in-system programmable applications.
®
®
®
ARM
Thumb
Processor Core
AT91
®
ARM
Thumb
Microcontrollers
AT91FR40162S
Preliminary
6174B–ATARM–07-Nov-05
®

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Summary of Contents for Atmel AT91FR40162S

  • Page 1: Features

    Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch 1. Description The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption.

  • Page 2: Pin Configuration

    2. Pin Configuration Figure 2-1. AT91FR40162S Pinout for 121-ball BGA Package (Top View) A1 Corner P21/TXD1 VDDCORE NTRI RXD0 IRQ2 TIOB2 TCLK2 TIOB0 VDDIO RXD1 SCK1 IRQ1 TIOA2 TIOA1 TIOA0 NBUSY VDDIO NWR1 TXD0 IRQ0 TIOB1 TCLK1 TCLK0 MCKI NRST...

  • Page 3: Signal Description

    AT91FR40162S Preliminary 3. Signal Description Table 3-1. AT91FR40162S Signal Description Active Module Name Function Type Level Comments Valid after reset; do not reprogram A20 to A0 - A23 Address Bus Output – I/O, as it is MSB of Flash address...
  • Page 4 Table 3-1. AT91FR40162S Signal Description (Continued) Active Module Name Function Type Level Comments NCSF Flash Memory Select Input Enables Flash Memory when pulled low Flash NBUSY Flash Memory Busy Output Output Flash RDY/BUSY signal; open-drain Memory NRSTF Flash Memory Reset Input...

  • Page 5: Block Diagram

    AT91FR40162S Preliminary 4. Block Diagram Figure 4-1. AT91FR40162S 6174B–ATARM–07-Nov-05...

  • Page 6: Architectural Overview

    Memories The AT91FR40162S embeds 256K bytes of internal SRAM. The internal memory is directly con- nected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 67 MIPS at 75 MHz by using the ARM instruction set of the processor, minimiz- ing system power consumption and improving on the performance of separate memory solutions.
  • Page 7 AT91FR40162S Preliminary 5.2.1 System Peripherals The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8- or 16-bit databus and is programmed through the APB. Each chip select line has its own program- ming register. The Power-saving (PS) module implements the Idle Mode (ARM7TDMI core clock stopped until the next interrupt) and enables the user to adapt the power consumption of the microcontroller to application requirements (independent peripheral clock control).

  • Page 8: Product Overview

    Master Clock The AT91FR40162S has a fully static design and works on the Master Clock (MCK), provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multi- plexed with a general purpose I/O line.

  • Page 9: Emulation Functions

    6.5.1 Tri-state Mode The AT91FR40162S microcontroller provides a tri-state mode, which is used for debug pur- poses. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40008 microcontroller are disabled.

  • Page 10: Memory Controller

    6.6.1 Internal Memories The AT91FR40162S microcontroller integrates 256K bytes of internal SRAM. It is 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses are supported and are executed within one cycle. Fetching either Thumb or ARM instructions is sup- ported, and internal memory can store two times as many Thumb instructions as ARM instructions.
  • Page 11 Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91FR40162S uses a remap command that enables switching between the boot memory and the internal primary SRAM bank addresses.
  • Page 12 • Program Inhibit – holding any one of OE low, CE high or WE high inhibits program cycles. • Noise Filter – pulses of less than a certain duration on the WE or CE inputs will not initiate a program cycle. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 13: At91 Flash Memory Uploader (Fmu) Software

    6.7.1 Flash Memory Uploader Operations The Flash Memory Uploader requires the encapsulated Flash to be used as the AT91FR40162S boot memory and a valid clock to be applied to MCKI. After reset, the Flash Memory Uploader immediately recopies itself into the internal SRAM and jumps to it. The following operation requires this memory resource only.
  • Page 14 Note that in the event that the Flash Memory Uploader is erased from the first sector while the new final application is not yet programmed, and while the target system power supply is switched off, it leads to a non-recoverable error and the AT91FR40162S cannot be re-pro- grammed by using the Flash Memory Uploader.

  • Page 15: Peripherals

    7.0.3 Peripheral Data Controller The AT91FR40162S has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of each USART. The user interface of a PDC channel is integrated in the memory space of each USART. It con- tains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer Counter Register (RCR or TCR).

  • Page 16: System Peripherals

    7.1.3 PIO: Parallel I/O Controller The AT91FR40162S has 32 programmable I/O lines. Six pins are dedicated as general-purpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins.

  • Page 17: User Peripherals

    7.2.2 TC: Timer Counter The AT91FR40162S features a Timer Counter block that includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse gen- eration, delay timing and pulse width modulation.

  • Page 18: Memory Map

    8. Memory Map Figure 8-1. AT91FR40162S Memory Map Before and After the Remap Command Before After Address Function Size Abort Control Address Function Size Abort Control 0xFFFFFFFF 0xFFFFFFFF On-chip On-chip 4M Bytes 4M Bytes Peripherals Peripherals 0xFFC00000 0xFFC00000 0xFFBFFFFF 0xFFBFFFFF...

  • Page 19: Peripheral Memory Map

    AT91FR40162S Preliminary 9. Peripheral Memory Map Figure 9-1. Peripheral Memory Map Address Peripheral Peripheral Name Size 0xFFFFFFFF Advanced Interrupt Controller 4K Bytes 0xFFFFF000 Reserved 0xFFFFBFFF WatchdogTimer 16K Bytes 0xFFFF8000 0xFFFF7FFF 16K Bytes Power Saving 0xFFFF4000 0xFFFF3FFF Parallel I/O Controller 16K Bytes...

  • Page 20: Ebi: External Bus Interface

    If two chip selects are defined as having the same base address, an access to the overlapping address space asserts both NCS lines. The Chip Select Register with the smaller number defines the characteristics of the external access and the behavior of the control signals. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 21: External Bus Interface Pin Description

    AT91FR40162S Preliminary Figure 10-1. External Memory Smaller than Page Size Base + 4M Bytes 1M Byte Device Repeat 3 Base + 3M Bytes 1M Byte Device Repeat 2 Memory Base + 2M Bytes 1M Byte Device Repeat 1 Base + 1M Bytes...

  • Page 22: Chip Select Lines

    NCS1 Memory Enable NCS0 Memory Enable Output Enable Write Enable A0 - A19 8 or 16 D0 - D15 or D0 - D7 Note: For eight external devices, the maximum address space per device is 1M byte. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 23: Data Bus Width

    AT91FR40162S Preliminary 10.4 Data Bus Width A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the EBI_CSR (Chip Select Register) for the corresponding chip select.

  • Page 24: Byte Write Or Byte Select Access

    • The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write operations. • The signal NWR0/NWE is used as NWE and enables writing for byte or half word. • The signal NRD/NOE is used as NOE and enables reading for byte or half word. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 25 AT91FR40162S Preliminary Figure 10-7 shows how to connect a 16-bit device with byte and half-word access (e.g. 16-bit SRAM) on NCS2. Figure 10-7. Connection for a 16-bit Data Bus with Byte and Half-word Access D0 - D7 D0 - D7...

  • Page 26: Boot On Ncs0

    (see Figure 10-11). This wait state is generated in addition to any other pro- grammed wait states (i.e. data float wait). AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 27 AT91FR40162S Preliminary No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Early read wait states affect the external bus only. They do not affect internal bus timing.

  • Page 28: Write Data Hold Time

    Figure 10-12. Data Hold Time ADDR Data Output In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a write access. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 29: Wait States

    AT91FR40162S Preliminary 10.9 Wait States The EBI can automatically insert wait states. The different types of wait states are listed below: • Standard wait states • Data float wait states • External wait states • Chip select change wait states •...
  • Page 30 If NWAIT is low at the rising edge of the clock, the EBI adds a wait state and changes neither the output signals nor its internal counters and state. When NWAIT is de-asserted, the EBI finishes the access sequence. The NWAIT signal must meet setup and hold requirements on the rising edge of the clock. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 31 AT91FR40162S Preliminary Figure 10-15. External Wait ADDR NWAIT Notes: 1. Early Read Protocol 2. Standard Read Protocol 10.9.4 Chip Select Change Wait States A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no wait states have already been inserted). If any wait states have already been inserted, (e.g., data float wait) then none are added.

  • Page 32: Memory Access Waveforms

    10.10 Memory Access Waveforms Figure 10-17 through Figure 10-20 show examples of the two alternative protocols for external memory read access. Figure 10-17. Standard Read Protocol without t AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 33 AT91FR40162S Preliminary Figure 10-18. Early Read Protocol Without t 6174B–ATARM–07-Nov-05...
  • Page 34 Figure 10-19. Standard Read Protocol with t AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 35 AT91FR40162S Preliminary Figure 10-20. Early Read Protocol With t 6174B–ATARM–07-Nov-05...
  • Page 36 Figure 10-21 through Figure 10-27 show the timing cycles and wait states for read and write access to the various AT91FR40162S external memory devices. The configurations described are shown in the following table: Table 10-3. Memory Access Waveforms Figure Number...
  • Page 37 AT91FR40162S Preliminary Figure 10-21. 0 Wait States, 16-bit Bus Width, Word Transfer ADDR ADDR+1 A1 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus X X B · Early Protocol D0 - D15 WRITE ACCESS · Byte Write/...
  • Page 38 1 Wair State ADDR ADDR+1 A1 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus X X B · Early Protocol D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option D0 - D15 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 39 AT91FR40162S Preliminary Figure 10-23. 1 Wait State, 16-bit Bus Width, Half-word Transfer 1 Wait State A1 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus X X B · Early Protocol D0 - D15 WRITE ACCESS ·...
  • Page 40 Figure 10-24. 0 Wait States, 8-bit Bus Width, Word Transfer ADDR ADDR+1 ADDR+2 ADDR+3 A0 - A23 READ ACCESS · Standard Protocol D0-D15 Internal Bus X X X B X X B · Early Protocol D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 41 AT91FR40162S Preliminary Figure 10-25. 1 Wait State, 8-bit Bus Width, Half-word Transfer 1 Wait State 1 Wait State ADDR ADDR+1 A0 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus X X X B X X B ·...
  • Page 42 Figure 10-26. 1 Wait State, 8-bit Bus Width, Byte Transfer 1 Wait State A0 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus X X X B · Early Protocol D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 43 AT91FR40162S Preliminary Figure 10-27. 0 Wait States, 16-bit Bus Width, Byte Transfer ADDR X X X 0 A1 - A23 ADDR X X X 0 Internal Address ADDR X X X 0 ADDR X X X 1 READ ACCESS ·...

  • Page 44: Ebi User Interface

    Chip Select Register 7 EBI_CSR7 Read/Write 0x70000000 0x20 Remap Control Register EBI_RCR Write-only – 0x24 Memory Control Register EBI_MCR Read/Write Notes: 1. 8-bit boot (if BMS is detected high) 2. 16-bit boot (if BMS is detected low) AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 45 AT91FR40162S Preliminary 10.11.1 EBI Chip Select Register Register Name: EBI_CSR0 - EBI_CSR7 Access Type: Read/Write Reset Value: Table 10-4 on page 44 Absolute Address: 0xFFE00000 - 0xFFE0001C Offset: 0x00 - 0x1C – – – – – – CSEN PAGES –...
  • Page 46 • BA: Base Address (Code Label EBI_BA) These bits contain the highest bits of the base address. If the page size is larger than 1M byte, the unused bits of the base address are ignored by the EBI decoder. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 47 AT91FR40162S Preliminary 10.11.2 EBI Remap Control Register Register Name: EBI_RCR Access Type: Write-only Absolute Address: 0xFFE00020 Offset: 0x20 – – – – – – – – – – – – – – – – – – – – – –...
  • Page 48 1M Byte CS4, CS5, CS6, CS7 EBI_ALE_1M • DRP: Data Read Protocol Code Label Selected DRP EBI_DRP Standard read protocol for all external memory devices enabled EBI_DRP_STANDARD Early read protocol for all external memory devices enabled EBI_DRP_EARLY AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 49: Flash Memory

    AT91FR40162S Preliminary 11. Flash Memory The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see ”Sector Lockdown”...

  • Page 50: Block Diagram

    WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 51 AT91FR40162S Preliminary 11.2.3 Reset A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state.
  • Page 52 ”Status Bit Table” on page 60 for more details. The toggle bit status bit should be used in conjunction with the erase/program and V status bit as shown in the algorithm in Figures 11-4 and 11-5 page AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 53: Sector Lockdown

    AT91FR40162S Preliminary 11.2.10 Erase/Program Status Bit The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to verify that an erase or a byte/word program operation has been successfully performed.
  • Page 54 11.3.5 Product Identification The product identification mode identifies the device and manufacturer as Atmel. It is accessed using a software operation. For details, see “Software Product Identification Entry”...
  • Page 55 AT91FR40162S Preliminary cycles and is released at the completion of the cycle. The open-drain connection allows for OR- tying of several devices to the same RDY/BUSY line. See Table 11-1, “Status Bit Table,” on page 60 for more details. 11.3.8 Common Flash Interface (CFI) CFI is a published, standardized data structure that may be read from a flash device.
  • Page 56 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non- protected sector address. 2. I/O7 sqhould be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 57 AT91FR40162S Preliminary Figure 11-3. Data Polling Algorithm (Configuration Register = 01) START Read I/O7 - I/O0 Addr = VA I/O7 = Data? I/O3, I/O5 = 1? Read I/O7 - I/O0 Addr = VA I/O7 = Data? Program/Erase Program/Erase Operation Not...
  • Page 58 Successful, Write Successful, Product ID Device in Exit Command Read Mode Note: The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop tog- gling as I/O5 changes to “1”. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 59 AT91FR40162S Preliminary Figure 11-5. Toggle Bit Algorithm (Configuration Register = 01) START Read I/O7 - I/O0 Read I/O7 - I/O0 Toggle Bit = Toggle? I/O3, I/O5 = 1? Read I/O7 - I/O0 Twice Toggle Bit = Toggle? Program/Erase Program/Erase Operation Not...

  • Page 60: Status Bit Table

    1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a “1” when the V level is not high enough to successfully perform program and erase operations. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 61: Flash Memory Command Definitiion

    AT91FR40162S Preliminary 11.5 Flash Memory Command Definitiion Table 11-2. Command Definition Table 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Cycle Cycle Cycle Cycle Cycle Cycle Command Sequence Cycles Addr Data Addr Data Addr Data Addr...

  • Page 62: Protection Register Addressing

    Protection Register Addressing Table Word Block Factory Factory Factory Factory User User User User Note: 1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 63: Sector Address

    AT91FR40162S Preliminary 11.7 Sector Address Table 11-4. Sector Address Table Sector Size (Bytes/Words) Address Range (A19 - A-1) Address Range (A19 - A0) 8K/4K 000000 - 001FFF 00000 - 00FFF 8K/4K 002000 - 003FFF 01000 - 01FFF 8K/4K 004000 - 005FFF...

  • Page 64: Software Product Identification Entry

    3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH Device Code: 00C0H 6. Either one of the Product ID Exit commands can be used. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 65: Sector Lockdown Enable Algorithm

    AT91FR40162S Preliminary 11.10 Sector Lockdown Enable Algorithm Figure 11-8. Sector Lockdown Enable Algorithm LOAD DATA AA ADDRESS 555 LOAD DATA 55 ADDRESS AAA LOAD DATA 80 ADDRESS 555 LOAD DATA AA ADDRESS 555 LOAD DATA 55 ADDRESS AAA LOAD DATA 60 SECTOR ADDRESS PAUSE 200 µs...

  • Page 66: Common Flash Interface Definition

    64K bytes, Y = 30 0000h 64K bytes, Z = 256 0001h 64K bytes, Z = 256 0007h 8K bytes, Y = 7 0000h 8K bytes, Y = 7 0020h 8K bytes, Z = 32 0000h 8K bytes, Z = 32 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 67 AT91FR40162S Preliminary Table 11-5. Common Flash Interface Definition (Continued) Address Address [x16 Mode] [x8 Mode] Data Comments Vendor Specific Extended Query 0050h “P” 0052h “R” 0049h “I” 0031h Major version number, ASCII 0030h Minor version number, ASCII Bit 0 – chip erase supported, 0 – no, 1 – yes Bit 1 –...

  • Page 68: Ps: Power-Saving

    12.1 Peripheral Clocks The clock of each peripheral integrated in the AT91FR40162S can be individually enabled and disabled by writing to the Peripheral Clock Enable (PS_PCER) and Peripheral Clock Disable Registers (PS_PCDR). The status of the peripheral clocks can be read in the Peripheral Clock Status Register (PS_PCSR).

  • Page 69: Power Saving (Ps) User Interface

    AT91FR40162S Preliminary 12.2 Power Saving (PS) User Interface Base Address: 0xFFFF4000 (Code Label PS_BASE) Table 12-1. PS Memory Map Offset Register Name Access Reset State 0x00 Control Register PS_CR Write-only – 0x04 Peripheral Clock Enable Register PS_PCER Write-only – 0x08...
  • Page 70 – – – – – – – – – • CPU: CPU Clock Disable 0 = No effect. 1 = Disables the CPU clock. The CPU clock is re-enabled by any enabled interrupt or by hardware reset. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 71 AT91FR40162S Preliminary 12.2.2 PS Peripheral Clock Enable Register Name: PS_PCER Access: Write-only Offset: 0x04 – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 72 1 = Disables the Timer Counter 1 clock. • TC2: Timer Counter 2 Clock Disable 0 = No effect. 1 = Disables the Timer Counter 2 clock. • PIO: Parallel IO Clock Disable 0 = No effect. 1 = Disables the Parallel IO clock. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 73 AT91FR40162S Preliminary 12.2.4 PS Peripheral Clock Status Register Name: PS_PCSR Access: Read-only Reset Value: 0x17C Offset: 0x0C – – – – – – – – – – – – – – – – – – – – – – –...

  • Page 74: Aic: Advanced Interrupt Controller

    13. AIC: Advanced Interrupt Controller The AT91FR40162S has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor.
  • Page 75 AT91FR40162S Preliminary Table 13-1. AIC Interrupt Sources Interrupt Source Interrupt Name Interrupt Description Fast Interrupt SWIRQ Software Interrupt US0IRQ USART Channel 0 interrupt US1IRQ USART Channel 1 interrupt TC0IRQ Timer Channel 0 interrupt TC1IRQ Timer Channel 1 interrupt TC2IRQ Timer Channel 2 interrupt...

  • Page 76: Hardware Interrupt Vectoring

    This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs. At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR) must be written. This allows pending interrupts to be serviced. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 77: Interrupt Masking

    AT91FR40162S Preliminary 13.5 Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR. The interrupt mask can be read in the read-only register AIC_IMR. A disabled interrupt does not affect the servicing of other interrupts.

  • Page 78: Protect Mode

    The debug system must not write to the AIC_IVR as this would cause undesirable effects. The following table shows the main steps of an interrupt and the order in which they are per- formed according to the mode: AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 79: Standard Interrupt Sequence

    AT91FR40162S Preliminary Table 13-2. Order of Interrupt Steps According to Mode Action Normal Mode Protect Mode Calculate active interrupt (higher than current or spurious) Read AIC_IVR Read AIC_IVR Determine and return the vector of the active interrupt Read AIC_IVR Read AIC_IVR...

  • Page 80: Fast Interrupt Sequence

    NFIQ line. 6. Finally, the Link Register (r14_fiq) is restored into the PC after decrementing it by 4 (with instruction sub pc, lr, #4 for example). This has effect of returning from the inter- AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 81 AT91FR40162S Preliminary rupt to whatever was being executed before, and of loading the CPSR with the SPSR, masking or unmasking the fast interrupt depending on the state saved in the SPSR. The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted.

  • Page 82: Aic User Interface

    End of Interrupt Command Register AIC_EOICR Write-only – 0x134 Spurious Vector Register AIC_SPU Read/Write Note: 1. The reset value of this register depends on the level of the External IRQ lines. All other sources are cleared at reset. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 83 AT91FR40162S Preliminary 13.13.1 AIC Source Mode Register Register Name: AIC_SMR0 - AIC_SMR31 Access Type: Read/Write Reset Value: Offset: 0x000 - 0x07C – – – – – – – – – – – – – – – – – – –...
  • Page 84 The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the IRQ Vector Register reads 0. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 85 AT91FR40162S Preliminary 13.13.4 AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read-only Reset Value: Offset: 0x104 FIQV FIQV FIQV FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 which corresponds to FIQ.
  • Page 86 – – – – IRQ2 IRQ1 IRQ0 – – – – – – – PIOIRQ WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ • Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 87 AT91FR40162S Preliminary 13.13.8 AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only Reset Value: Offset: 0x114 – – – – – – – – – – – – – – – – – – – – – –...
  • Page 88 – – – – – – – IRQ2 IRQ1 IRQ0 – – – – – – – PIOIRQ WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ • Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 89 AT91FR40162S Preliminary 13.13.12 AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only Offset: 0x12C – – – – – – – – – – – – – IRQ2 IRQ1 IRQ0 – – – – – – – PIOIRQ...
  • Page 90 13.13.14 AIC Spurious Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: Offset: 0x134 SPUVEC SPUVEC SPUVEC SPUVEC • SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 91: Pio: Parallel I/O Controller

    AT91FR40162S Preliminary 14. PIO: Parallel I/O Controller The AT91FR40162S has 32 programmable I/O lines. Six pins are dedicated as general purpose I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed with an external sig- nal of a peripheral to optimize the use of available package pins (see Table 14-1 on page 94).

  • Page 92: Interrupts

    Each individual I/O is associated with a bit position in the Parallel I/O user interface registers. Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corre- sponding bits has no effect. Undefined bits read zero. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 93 AT91FR40162S Preliminary Figure 14-1. Parallel I/O Multiplexed with a Bi-directional Signal PIO_OSR Pad Output Enable Peripheral Output Enable PIO_PSR PIO_ODSR Pad Output Peripheral Output Pad Input Peripheral Input PIO_PSR PIO_PDSR Event Detection PIO_ISR PIO_IMR PIOIRQ 6174B–ATARM–07-Nov-05...
  • Page 94 Address 21/Chip Select 6 Output A22/CS5 Address 22/Chip Select 5 Output A23/CS4 Address 23/Chip Select 4 Output Note: 1. Bit Number refers to the data bit that corresponds to this signal in each of the User Interface registers. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 95: Pio User Interface

    AT91FR40162S Preliminary 14.6 PIO User Interface PIO Base Address: 0xFFFF0000 (Code Label PIO_BASE) Table 14-2. PIO Controller Memory Map Offset Register Name Access Reset State 0x00 PIO Enable Register PIO_PER Write-only – 0x04 PIO Disable Register PIO_PDR Write-only – 0x01FFFFFF...
  • Page 96 This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func- tion is enabled on the corresponding pin. 1 = Disables PIO control (enables peripheral control) on the corresponding pin. 0 = No effect. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 97 AT91FR40162S Preliminary 14.6.3 PIO Status Register Register Name: PIO_PSR Access Type: Read-only Reset Value: 0x01FFFFFF Offset: 0x08 This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or disabled. 1 = PIO is active on the corresponding line (peripheral is inactive).
  • Page 98 PIO. The register reads as follows: 1 = The corresponding PIO is output on this line. 0 = The corresponding PIO is input on this line. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 99 AT91FR40162S Preliminary 14.6.7 PIO Input Filter Enable Register Register Name: PIO_IFER Access Type: Write-only Offset: 0x20 This register is used to enable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is pro- grammed as follows: 1 = Enables the glitch filter on the corresponding pin.
  • Page 100 This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is set. 0 = No effect. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 101 AT91FR40162S Preliminary 14.6.11 PIO Clear Output Data Register Register Name: PIO_CODR Access Type: Write-only Offset: 0x34 This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO.
  • Page 102 This register is used to enable PIO interrupts on the corresponding pin. It has effect whether PIO is enabled or not. 1 = Enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = No effect. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 103 AT91FR40162S Preliminary 14.6.15 PIO Interrupt Disable Register Register Name: PIO_IDR Access Type: Write-only Offset: 0x44 This register is used to disable PIO interrupts on the corresponding pin. It has effect whether the PIO is enabled or not. 1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected.
  • Page 104 The register is reset to zero following a read, and at reset. 1 = At least one change has been detected on the corresponding pin since the register was last read. 0 = No change has been detected on the corresponding pin since the register was last read. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 105: Wd: Watchdog Timer

    AT91FR40162S Preliminary 15. WD: Watchdog Timer The AT91FR40162S has an internal watchdog timer which can be used to prevent system lock- up if the software becomes trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer overflow occurs. If an overflow does occur, the...

  • Page 106: Wd Enabling Sequence

    This step is unnecessary if the WD is already disabled (reset state). 2. Initialize the WD Clock Mode Register: Write 0x373C to WD_CMR (HPCV = 15 and WDCLKS = MCK/8) 3. Restart the timer: Write 0xC071 to WD_CR 4. Enable the watchdog: Write 0x2345 to WD_OMR (interrupt enabled) AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 107: Wd User Interface

    AT91FR40162S Preliminary 15.3 WD User Interface WD Base Address: 0xFFFF8000 (Code Label WD_BASE) Table 15-1. WD Memory Map Offset Register Name Access Reset State 0x00 Overflow Mode Register WD_OMR Read/Write 0x04 Clock Mode Register WD_CMR Read/Write 0x08 Control Register WD_CR Write-only –...
  • Page 108 1 = When an overflow occurs, a pulse on the pin NWDOVF is generated. • OKEY: Overflow Access Key (Code Label WD_OKEY) Used only when writing WD_OMR. OKEY is read as 0. 0x234 = Write access in WD_OMR is allowed. Other value = Write access in WD_OMR is prohibited. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 109 AT91FR40162S Preliminary 15.3.2 WD Clock Mode Register Name: WD_CMR Access: Read/Write Reset Value: Offset: 0x04 – – – – – – – – – – – – – – – – CKEY – CKEY HPCV WDCLKS • WDCLKS: Clock Selection...
  • Page 110 – – – WDOVF • WDOVF: Watchdog Overflow (Code Label WD_WDOVF) 0 = No watchdog overflow. 1 = A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 111: Sf: Special Function Registers

    AT91FR40162S Preliminary 16. SF: Special Function Registers The AT91FR40162S provides registers to implement the following special functions. • Chip identification • RESET status • Protect Mode (see Section 13.10 ”Protect Mode”, on page 16.1 Chip Identification Table 16-1 provides the Chip ID values for the products as listed.

  • Page 112: Sf User Interface

    Chip ID Register SF_CIDR Read-only Hardwired 0x04 Chip ID Extension Register SF_EXID Read-only Hardwired 0x08 Reset Status Register SF_RSR Read-only See register description 0x10 Reserved – – – 0x14 Reserved – – – 0x18 Protect Mode Register SF_PMR Read/Write AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 113 AT91FR40162S Preliminary 16.2.1 Chip ID Register Register Name: SF_CIDR Access Type: Read-only Reset Value: Hardwired Offset: 0x00 NVPTYP ARCH ARCH VDSIZ NVDSIZ NVPSIZ VERSION • VERSION: Version of the chip (Code Label SF_VERSION) This value is incremented by one with each new version of the chip (from zero to a maximum value of 31).
  • Page 114 SF_NVPTYP_M Reserved – “R” Series SF_NVPTYP_R • EXT: Extension Flag (Code Label SF_EXT) 0 = Chip ID has a single register definition without extensions 1 = An extended Chip ID exists (to be defined in the future). AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 115 AT91FR40162S Preliminary 16.2.2 Chip ID Extension Register Register Name: SF_EXID Access Type: Read-only Reset Value: Hardwired Offset: 0x04 This register is reserved for future use. It will be defined when needed. 16.2.3 Reset Status Register Register Name: SF_RSR Access Type:...
  • Page 116 Other value: Write access in SF_PMR is prohibited. • AIC: AIC Protect Mode Enable (Code Label SF_AIC) 0 = The Advanced Interrupt Controller runs in Normal Mode. 1 = The Advanced Interrupt Controller runs in Protect Mode. Section 13.10 ”Protect Mode”, on page AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 117: Usart: Universal Synchronous Asynchronous Receiver Transmitter

    AT91FR40162S Preliminary 17. USART: Universal Synchronous Asynchronous Receiver Transmitter The AT91FR40162S provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator •...

  • Page 118: Pin Description

    ”PIO: Parallel I/O Controller” on page 91). The user must configure the PIO Controller before enabling the transmitter or receiver. 2. If the user selects one of the internal clocks, SCK can be configured as a PIO. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 119: Baud Rate Generator

    AT91FR40162S Preliminary 17.3 Baud Rate Generator The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the Receiver and the Transmitter. The Baud Rate Generator can select between external and internal clock sources. The external clock source is SCK.

  • Page 120: Receiver

    Baud Rate clock. If a low level is detected, it is considered as a start. Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. See example in Figure 17-5. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 121 AT91FR40162S Preliminary Figure 17-5. Synchronous Mode: Character Reception Example: 8-bit, parity enabled 1 stop Sampling Stop Bit True Start Detection Parity Bit 17.4.3 Receiver Ready When a complete character is received, it is transferred to the US_RHR and the RXRDY status bit in US_CSR is set.

  • Page 122: Transmitter

    (SENDA) is written to US_CR. In this case, the next byte written to US_THR will be transmitted as an address. After this any byte transmitted will have the parity bit cleared. Figure 17-6. Synchronous and Asynchronous Modes: Character Transmission Example: 8-bit, parity enabled 1 stop Baud Rate Clock Start Parity Stop AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 123: Break

    AT91FR40162S Preliminary 17.6 Break A break condition is a low signal level which has a duration of at least one character (including start/stop bits and parity). 17.6.1 Transmit Break The transmitter generates a break condition on the TXD line when STTBRK is set in US_CR (Control Register).
  • Page 124 2/16 of a bit period in Asynchronous Mode or at least one sample in Synchronous Mode. RXBRK is also asserted when an end of break is detected. Both the beginning and the end of a break can be detected by interrupt if the bit US_IMR.RXBRK is set. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 125: Peripheral Data Controller

    AT91FR40162S Preliminary 17.7 Peripheral Data Controller Each USART channel is closely connected to a corresponding Peripheral Data Controller chan- nel. One is dedicated to the receiver. The other is dedicated to the transmitter. Note: The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR.

  • Page 126: Channel Modes

    Remote Loopback Mode directly connects the RXD pin to the TXD pin. The Transmitter and the Receiver are disabled and have no effect. This mode allows bit by bit re-transmission. Figure 17-7. Channel Modes Automatic Echo Receiver Disabled Transmitter Local Loopback Disabled Receiver Disabled Transmitter Remote Loopback Disabled Receiver Disabled Transmitter AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 127: Usart User Interface

    AT91FR40162S Preliminary 17.10 USART User Interface Base Address USART0: 0xFFFD0000 (Code Label USART0_BASE) Base Address USART1: 0xFFFCC000 (Code Label USART1_BASE) Table 17-2. USART Memory Map Offset Register Name Access Reset State 0x00 Control Register US_CR Write-only – 0x04 Mode Register...
  • Page 128 • STTBRK: Start Break (Code Label US_STTBRK) 0 = No effect. 1 = If break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 129 AT91FR40162S Preliminary • STPBRK: Stop Break (Code Label US_STPBRK) 0 = No effect. 1 = If a break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods.
  • Page 130 US_CHRL_7 Eight bits US_CHRL_8 Start, stop and parity bits are added to the character length. • SYNC: Synchronous Mode Select (Code Label US_SYNC) 0 = USART operates in Asynchronous Mode. 1 = USART operates in Synchronous Mode. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 131 AT91FR40162S Preliminary • PAR: Parity Type Code Label Parity Type US_PAR Even Parity US_PAR_EVEN Odd Parity US_PAR_ODD Parity forced to 0 (Space) US_PAR_SPACE Parity forced to 1 (Mark) US_PAR_MARK No parity US_PAR_NO Multi-drop mode US_PAR_MULTIDROP • NBSTOP: Number of Stop Bits The interpretation of the number of stop bits depends on SYNC.
  • Page 132 • FRAME: Enable Framing Error Interrupt (Code Label US_FRAME) 0 = No effect. 1 = Enables Framing Error Interrupt. • PARE: Enable Parity Error Interrupt (Code Label US_PARE) 0 = No effect. 1 = Enables Parity Error Interrupt. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 133 AT91FR40162S Preliminary • TIMEOUT: Enable Time-out Interrupt (Code Label US_TIMEOUT) 0 = No effect. 1 = Enables Reception Time-out Interrupt. • TXEMPTY: Enable TXEMPTY Interrupt (Code Label US_TXEMPTY) 0 = No effect. 1 = Enables TXEMPTY Interrupt. 6174B–ATARM–07-Nov-05...
  • Page 134 • FRAME: Disable Framing Error Interrupt (Code Label US_FRAME) 0 = No effect. 1 = Disables Framing Error Interrupt. • PARE: Disable Parity Error Interrupt (Code Label US_PARE) 0 = No effect. 1 = Disables Parity Error Interrupt. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 135 AT91FR40162S Preliminary • TIMEOUT: Disable Time-out Interrupt (Code Label US_TIMEOUT) 0 = No effect. 1 = Disables Receiver Time-out Interrupt. • TXEMPTY: Disable TXEMPTY Interrupt (Code Label US_TXEMPTY) 0 = No effect. 1 = Disables TXEMPTY Interrupt. 6174B–ATARM–07-Nov-05...
  • Page 136 0 = Framing Error Interrupt is Disabled 1 = Framing Error Interrupt is Enabled • PARE: Mask Parity Error Interrupt (Code Label US_PARE) 0 = Parity Error Interrupt is Disabled 1 = Parity Error Interrupt is Enabled AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 137 AT91FR40162S Preliminary • TIMEOUT: Mask Time-out Interrupt (Code Label US_TIMEOUT) 0 = Receive Time-out Interrupt is Disabled 1 = Receive Time-out Interrupt is Enabled • TXEMPTY: Mask TXEMPTY Interrupt (Code Label US_TXEMPTY) 0 = TXEMPTY Interrupt is Disabled. 1 = TXEMPTY Interrupt is Enabled.
  • Page 138 • FRAME: Framing Error (Code Label US_FRAME) 0 = No stop bit has been detected low since the last “Reset Status Bits” command. 1 = At least one stop bit has been detected low since the last “Reset Status Bits” command. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 139 AT91FR40162S Preliminary • PARE: Parity Error (Code Label US_PARE) 1 = At least one parity bit has been detected false (or a parity bit high in Multi-drop Mode) since the last “Reset Status Bits” command. 0 = No parity bit has been detected false (or a parity bit high in Multi-drop Mode) since the last “Reset Status Bits”...
  • Page 140 – – TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 141 AT91FR40162S Preliminary 17.10.9 USART Baud Rate Generator Register Name: US_BRGR Access Type: Read/Write Reset Value: Offset: 0x20 – – – – – – – – – – – – – – – – • CD: Clock Divisor This register has no effect if Synchronous Mode is selected with an external clock.
  • Page 142 The Time-out counter is loaded with TO when the Start Time-out Command is given or when each new data character is 1 - 255 received (after reception has started). Time-out duration = TO x 4 x Bit period AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 143 AT91FR40162S Preliminary 17.10.11 USART Transmitter Time-guard Register Name: US_TTGR Access Type: Read/Write Reset Value: Offset: 0x28 – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 144 1 - 65535: Start Peripheral Data transfer if RXRDY is active. 17.10.14 USART Transmit Pointer Register Name: US_TPR Access Type: Read/Write Reset Value: Offset: 0x38 TXPTR TXPTR TXPTR TXPTR • TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 145 AT91FR40162S Preliminary 17.10.15 USART Transmit Counter Register Name: US_TCR Access Type: Read/Write Reset Value: Offset: 0x3C – – – – – – – – – – – – – – – – TXCTR TXCTR • TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer.

  • Page 146: Tc: Timer Counter

    18. TC: Timer Counter The AT91FR40162S features a Timer Counter block which includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse gen- eration, delay timing and pulse width modulation.

  • Page 147: Block Diagram

    AT91FR40162S Preliminary 18.1 Block Diagram Figure 18-1. TC Block Diagram Parallel IO Controller MCK/2 TCLK0 TCLK0 TCLK1 TCLK2 MCK/8 TIOA1 TIOA2 Timer Counter MCK/32 TIOA TIOA0 Channel 0 TCLK1 TIOA0 TIOB0 TIOB TCLK2 TIOB0 MCK/128 TC0XC0S SYNC MCK/1024 TCLK0 TCLK1...

  • Page 148: Signal Description

    The current value of the counter is accessible in real-time by reading TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 149 AT91FR40162S Preliminary 18.3.2 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode).
  • Page 150 A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 151 AT91FR40162S Preliminary • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.

  • Page 152: Capture Operating Mode

    • ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status Note: All the status bits are set when the corresponding event occurs and they are automatically cleared when the Status Register is read. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 153 AT91FR40162S Preliminary Figure 18-4. Capture Mode TCCLKS CLKSTA CLKEN CLKDIS CLKI MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 LDBSTOP LDBDIS BURST Register C Capture Capture Register A Register B Compare RC = 16-bit Counter SWTRG RESET SYNC Trig ABETRG CPCTRG ETRGEDG MTIOB...

  • Page 154: Waveform Operating Mode

    The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 155 AT91FR40162S Preliminary The tables below show which parameter in TC_CMR is used to define the effect of each event. Parameter TIOA Event ASWTRG Software Trigger AEEVT External Event ACPC RC Compare ACPA RA Compare Parameter TIOB Event BSWTRG Software Trigger...
  • Page 156 Register A Register B Register C ASWTRG Compare RA = Compare RB = Compare RC = 16-bit Counter RESET SWTRG BCPC SYNC Trig MTIOB BCPB CPCTRG EEVT TIOB BEEVT EEVTEDG ENETRG Edge Detector BSWTRG TIOB Timer Counter Channel AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 157: Tc User Interface

    AT91FR40162S Preliminary 18.6 TC User Interface TC Base Address: 0xFFFE0000 (Code Label TC_BASE) Table 18-2. TC Global Memory Map Offset Channel/Register Name Access Reset State 0x00 TC Channel 0 See Table 18-3 0x40 TC Channel 1 See Table 18-3 0x80...
  • Page 158 – – – – – – – – – – – SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 159 AT91FR40162S Preliminary 18.6.2 TC Block Mode Register Register Name: TC_BMR Access Type: Read/Write Reset Value: Offset: 0xC4 – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 160 • CLKDIS: Counter Clock Disable Command (Code Label TC_CLKDIS) 0 = No effect. 1 = Disables the clock. • SWTRG: Software Trigger Command (Code Label TC_SWTRG) 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 161 AT91FR40162S Preliminary 18.6.4 TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type: Read/Write Reset Value: Offset: 0x04 – – – – – – – – – – – – LDRB LDRA – – – WAVE = 0 CPCTRG...
  • Page 162 1 = Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection Code Label LDRA Edge TC_LDRA None TC_LDRA_EDGE_NONE Rising edge of TIOA TC_LDRA_RISING_EDGE Falling edge of TIOA TC_LDRA_FALLING_EDGE Each edge of TIOA TC_LDRA_BOTH_EDGE AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 163 AT91FR40162S Preliminary • LDRB: RB Loading Selection Code Label LDRB Edge TC_LDRB None TC_LDRB_EDGE_NONE Rising edge of TIOA TC_LDRB_RISING_EDGE Falling edge of TIOA TC_LDRB_FALLING_EDGE Each edge of TIOA TC_LDRB_BOTH_EDGE 6174B–ATARM–07-Nov-05...
  • Page 164 Selected BURST TC_BURST The clock is not gated by an external signal. TC_BURST_NONE XC0 is ANDed with the selected clock. TC_BURST_XC0 XC1 is ANDed with the selected clock. TC_BURST_XC1 XC2 is ANDed with the selected clock. TC_BURST_XC2 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 165 AT91FR40162S Preliminary • CPCSTOP: Counter Clock Stopped with RC Compare (Code Label TC_CPCSTOP) 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. • CPCDIS: Counter Clock Disable with RC Compare (Code Label TC_CPCDIS) 0 = Counter clock is not disabled when counter reaches RC.
  • Page 166 • AEEVT: External Event Effect on TIOA Code Label AEEVT Effect TC_AEEVT None TC_AEEVT_OUTPUT_NONE TC_AEEVT_SET_OUTPUT Clear TC_AEEVT_CLEAR_OUTPUT Toggle TC_AEEVT_TOGGLE_OUTPUT • ASWTRG: Software Trigger Effect on TIOA Code Label ASWTRG Effect TC_ASWTRG None TC_ASWTRG_OUTPUT_NONE TC_ASWTRG_SET_OUTPUT Clear TC_ASWTRG_CLEAR_OUTPUT Toggle TC_ASWTRG_TOGGLE_OUTPUT AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 167 AT91FR40162S Preliminary • BCPB: RB Compare Effect on TIOB Code Label BCPB Effect TC_BCPB None TC_BCPB_OUTPUT_NONE TC_BCPB_SET_OUTPUT Clear TC_BCPB_CLEAR_OUTPUT Toggle TC_BCPB_TOGGLE_OUTPUT • BCPC: RC Compare Effect on TIOB Code Label BCPC Effect TC_BCPC None TC_BCPC_OUTPUT_NONE TC_BCPC_SET_OUTPUT Clear TC_BCPC_CLEAR_OUTPUT Toggle TC_BCPC_TOGGLE_OUTPUT •...
  • Page 168 Read-only if WAVE = 0, Read/Write if WAVE = 1 Reset Value: Offset: 0x14 – – – – – – – – – – – – – – – – • RA: Register A (Code Label TC_RA) RA contains the Register A value in real-time. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 169 AT91FR40162S Preliminary 18.6.8 TC Register B Register Name: TC_RB Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 Reset Value: Offset: 0x18 – – – – – – – – – – – – – – –...
  • Page 170 • ETRGS: External Trigger Status (Code Label TC_ETRGS) 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 171 AT91FR40162S Preliminary • CLKSTA: Clock Enabling Status (Code Label TC_CLKSTA) 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror (Code Label TC_MTIOA) 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
  • Page 172 1 = Enables the RA Load Interrupt. • LDRBS: RB Loading (Code Label TC_LDRBS) 0 = No effect. 1 = Enables the RB Load Interrupt. • ETRGS: External Trigger (Code Label TC_ETRGS) 0 = No effect. 1 = Enables the External Trigger Interrupt. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 173 AT91FR40162S Preliminary 18.6.12 TC Interrupt Disable Register Register Name: TC_IDR Access Type: Write-only Offset: 0x28 – – – – – – – – – – – – – – – – – – – – – – – – ETRGS...
  • Page 174 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. • ETRGS: External Trigger (Code Label TC_ETRGS) 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 175: At91Fr40162S Electrical Characteristics

    AT91FR40162S Preliminary 19. AT91FR40162S Electrical Characteristics 19.1 Absolute Maximum Ratings Table 19-1. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maxi- Operating Temperature (Industrial) .. -40° C to + 85° C mum Ratings” may cause permanent damage to the device.

  • Page 176: At91R40008 Dc Characteristics

    = Output Current at high level. 2. Pin Group 1 = NUB/NWR1, NWE/NWR0, NOE/NRD1 3. Pin Group 2 = D0-D15, A0/NLB, A1-A19, P28/A20/CS7, P29/A21/CS6, P30/A22/CS5, P31/A23/CS4, NCS0, NCS1, P26/NCS2, P27/NCS3 4. Pin Group 3 = All Others AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 177: Flash Dc Characteristics

    AT91FR40162S Preliminary 19.3 Flash DC Characteristics Table 19-3. Flash DC Characteristics Symbol Parameter Condition Units Input Load Current = 0V to V µA Output Leakage Current = 0V to V µA CE = V - 0.3V to Standby Current CMOS µA...

  • Page 178: Power Consumption

    Idle All peripheral clocks deactivated 0.06 Note: 1. With two Wait States. Table 19-6. Power Consumption per Peripheral on VDDCORE Peripheral Consumption Unit PIO Controller 15.3 Timer/Counter Channel 15.0 µW/MHz Timer/Counter Block (3 Channels) 36.3 USART 27.8 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 179: Clock Waveforms

    AT91FR40162S Preliminary 19.6 Clock Waveforms Table 19-7. Master Clock Waveform Parameters Symbol Parameter Conditions Units 1/(t Oscillator Frequency 82.1 Oscillator Period 12.2 High Half-period Low Half-period Table 19-8. Clock Propagation Times Symbol Parameter Conditions Units = 0 pF MCKO Rising Edge Propagation Time...
  • Page 180 Figure 19-2. MCKO Relative to NRST NRST MCKO AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 181: Ac Characteristics

    AT91FR40162S Preliminary 20. AC Characteristics 20.1 Applicable Conditions and Derating Data 20.1.1 Conditions and Timing Results The delays are given as typical values in the following conditions: • V = 3.0V DDIO • V = 1.8V DDCORE • Ambient Temperature = 25° C •...
  • Page 182 Core Voltage Derating Factor Figure 20-2. Core Voltage Derating Factor Derating Factor for Typ Case is 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 Core Supply Voltage (V) AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 183 AT91FR40162S Preliminary 20.1.4 IO Voltage Derating Factor Figure 20-3. Derating Factor for Different V Power Supply Levels DDIO Derating Factor for Typ Case is 1 Voltage Level DDIO 6174B–ATARM–07-Nov-05...

  • Page 184: Peripheral Signals

    20-4, and as represented in Figure 20-5. Table 20-3. Timer Input Minimum Pulse Width Symbol Parameter Min Pulse Width Units TCLK/TIOA/TIOB Minimum Pulse Width Table 20-4. Timer Input Minimum Period Symbol Parameter Min Input Period Units TCLK/TIOA/TIOB Minimum Input Period AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 185 AT91FR40162S Preliminary Figure 20-5. Timer Input MCKI TIOA/ TIOB/ TCLK 20.2.3 Reset Signals A minimum pulse width is necessary, as shown in Table 20-5 and as represented in Figure 20-6. Table 20-5. Reset Minimum Pulse Width Symbol Parameter Min Pulse-width...
  • Page 186 TCK High Half-period 22.7 TCK Period 46.1 TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High = 0 pF TDO Hold Time derating 0.001 ns/pF = 0 pF TCK Low to TDO Valid derating 0.28 ns/pF AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 187 AT91FR40162S Preliminary Figure 20-9. ICE Interface Signal NTRST TMS/TDI 6174B–ATARM–07-Nov-05...

  • Page 188: Ebi Signals Relative To Mcki

    = 0 pF NWR High to NLB/A0 Change derating 0.043 0.073 ns/pF = 0 pF NWR High to A1 - A23 Change derating 0.043 0.076 ns/pF = 0 pF NWR High to Chip Select Inactive derating 0.052 0.067 ns/pF AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 189 AT91FR40162S Preliminary Table 20-11. EBI Write Signals (Continued) Symbol Parameter Conditions Units C = 0 pF - 1.8 Data Out Valid before NWR High (No Wait States) derating -0.080 ns/pF DATA derating 0.044 ns/pF C = 0 pF n x t - 1.3...
  • Page 190 • Standard Read Protocol: Programming an additional t Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 191 AT91FR40162S Preliminary Figure 20-10. EBI Signals Relative to MCKI MCKI A1 - A23 NWAIT /EBI NUB/NLB/A0 27-30 D0 - D15 Read 12-15 NWR (No Wait States) NWR (Wait States) D0 - D15 to Write No Wait Wait Notes: 1. Early Read Protocol.

  • Page 192: Ac Flash Read Characteristics

    CE without impact on t or by t after an address change without impact on t 3. t is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 193 AT91FR40162S Preliminary 20.4.2 Input Test Waveforms and Measurement Level Figure 20-12. Input Test Waveforms and Measurement Level < 5 ns 20.4.3 Output Test Load Figure 20-13. Output Test Load 20.4.4 Pin Capacitance Table 20-15. Pin Capacitance f = 1 MHz, T = 25°C...

  • Page 194: Ac Flash Byte/Word Load Waveforms

    Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High 20.5.1 WE Controlled Figure 20-14. WE Controlled AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 195 AT91FR40162S Preliminary 20.5.2 CE Controlled Figure 20-15. CE Controlled 6174B–ATARM–07-Nov-05...

  • Page 196: Flash Program Cycle Characteristics

    SEC1 Sector Erase Cycle Time (32K Word Sectors) seconds SEC2 Erase Suspend Time µs Program Suspend Time µs 20.6.1 Program Cycle Waveforms Figure 20-16. Program Cycle Waveforms PROGRAM CYCLE A0 - A19 ADDRESS INPUT DATA DATA AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 197 AT91FR40162S Preliminary 20.6.2 Sector or Chip Erase Cycle Waveforms Figure 20-17. Sector or Chip Erase Cycle Waveforms A0-A19 Note 2 DATA Note 3 WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 Notes: 1. OE must be high only when WE and CE are both low.

  • Page 198: Flash Data Polling Characteristics

    Write Recovery Time Notes: 1. These parameters are characterized and not 100% tested. 2. See t spec in ”AC Flash Read Characteristics” on page 192. 20.7.1 Data Polling Waveforms Figure 20-18. Data Polling Waveforms HIGH Z I/O7 A0-A19 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 199: Flash Toggle Bit Characteristics

    AT91FR40162S Preliminary 20.8 Flash Toggle Bit Characteristics Table 20-19. Toggle Bit Characteristics Symbol Parameter Units Data Hold Time OE Hold Time OE to Output Delay OE High Pulse OEHP Write Recovery Time Notes: 1. These parameters are characterized and not 100% tested.

  • Page 200: Mechanical Characteristics

    From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature T in °C AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 201: Package Drawing

    AT91FR40162S Preliminary 21.2 Package Drawing Figure 21-1. AT91FR40162S Package Table 21-1. Thermal Resistance Data Symbol Parameter Condition Package Units θ Junction-to-ambient thermal resistance Still Air 121-BGA ° C/W θ Junction-to-case thermal resistance 121-BGA Table 21-2. Device and 121-ball BGA Package Maximum Weight Table 21-3.

  • Page 202: Soldering Profile

    6 ° C/sec. Ramp-down Rate Time 25 ° C to Peak Temperature 8 min. max Note: It is recomended to apply a soldering temperature higher than 250°C. A maximum of three reflow passes is allowed per component. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 203: Ordering Information

    AT91FR40162S Preliminary 22. Ordering Information Table 22-1. Ordering Information Temperature Ordering Code Package Package Type Operating Range Industrial AT91FR40162S-CJ BGA 121 RoHS (-40 ° C to 85 ° C) 6174B–ATARM–07-Nov-05...

  • Page 204: At91Fr40162S Errata

    23. AT91FR40162S Errata There is no known errata for the AT91FR40162S. AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 205: Table Of Contents

    AT91FR40162S Preliminary Table of Contents Features ..................... 1 Description ....................1 Pin Configuration ..................2 Signal Description ................... 3 Block Diagram ..................5 Architectural Overview ................6 5.1 Memories .........................6 5.2 Peripherals ......................6 Product Overview ..................8 6.1 Power Supply ......................8 6.2 Input/Output Considerations ..................8...
  • Page 206 13.10 Protect Mode .....................78 13.11 Standard Interrupt Sequence ................79 13.12 Fast Interrupt Sequence ..................80 13.13 AIC User Interface .....................82 14 PIO: Parallel I/O Controller ..............91 14.1 Multiplexed I/O Lines ...................91 14.2 Output Selection ....................91 14.3 I/O Levels ......................91 AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...
  • Page 207 18.3 Timer Counter Description ................148 18.4 Capture Operating Mode ...................152 18.5 Waveform Operating Mode ................154 18.6 TC User Interface ....................157 19 AT91FR40162S Electrical Characteristics ......... 175 19.1 Absolute Maximum Ratings ................175 19.2 AT91R40008 DC Characteristics ..............176 19.3 Flash DC Characteristics ...................177 19.4 Flash Operating Modes ..................177...
  • Page 208 20.8 Flash Toggle Bit Characteristics ................199 21 Mechanical Characteristics ..............200 21.1 Thermal Considerations ..................200 21.2 Package Drawing ....................201 21.3 Soldering Profile ....................202 22 Ordering Information ................203 23 AT91FR40162S Errata ................204 Table of Contents ..................i Revision History..................v AT91FR40162S Preliminary 6174B–ATARM–07-Nov-05...

  • Page 209: Revision History

    AT91FR40162S Preliminary Revision History Doc. Rev. Date Comments Change Request Ref. 6174A 20-Jun-05 First issue. Qualified on the Intranet - published on the web note removed Table 19-7 on page 179 CSR 05-447 6174B 07-Nov-05 Changes to Table 19-2 on page 176...
  • Page 210 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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