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Bit
Signal
0
CAL
5
WTG
8
CV
10
CC+
11
CC-
0
OV
1
OCP
4
OT
9
RI
10
Unreg
MeasOvld
14
0
OPC
2
QYE
3
DDE
4
EXE
5
CME
7
PON
3
QUES
4
MAV
5
ESB
6
MSS
RQS
7
OPER
Operation Status Group
The Operation Status registers record signals that occur during normal operation. As shown below, the
group consists of a Condition, PTR/NTR, Event, and Enable register. The outputs of the Operation Status
register group are logically-ORed into the OPERation summary bit (7) of the Status Byte register.
Register
Command
Condition
STAT:OPER:COND?
PTR Filter
STAT:OPER:PTR <n>
NTR Filter
STAT:OPER:NTR <n>
Event
STAT:OPER:EVEN?
Enable
STAT:OPER:ENAB <n>
Table 7-1. Bit Configurations of Status Registers
Meaning
Operation Status Group
The dc source is computing new calibration constants
The dc source is waiting for a trigger
The dc source is in constant voltage mode
The dc source is in constant current mode
The dc source is in negative constant current mode
Questionable Status Group
The overvoltage protection has tripped
The overcurrent protection has tripped
The overtemperature protection has tripped
The remote inhibit state is active
The output is unregulated
Current measurement exceeded capability of low range
Standard Event Status Group
Operation complete
Query error
Device-dependent error
Execution error
Command error
Power-on
Status Byte and Service Request Enable Registers
Questionable status summary bit
Message Available summary bit
Event Status Summary bit
Master Status Summary bit
Request Service bit
Operation status summary bit
A register that holds real-time status of the circuits being monitored.
It is a read-only register.
A positive transition filter that functions as described under
STAT:OPER:NTR|PTR commands in chapter 8. It is a read/write
register.
A negative transition filter that functions as described under
STAT:OPER:NTR|PTR commands in chapter 8. It is a read/write
register.
A register that latches any condition that is passed through the PTR or
NTR filters. It is a read-only register that is cleared when read.
A register that functions as a mask for enabling specific bits from the
Event register. It is a read/write register.
Programming the DC Source - 7
Description
71
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