Xilinx Virtex-II Pro ML324 User Manual page 24

Detailed Description
Table 18: Headers for the SDRAM Signals (Continued)
Pin Name
M1 VSSQ8
L9 VSSQ7
L8 DQ7
L7 VDD3
L3 VSS3
L2 DQ8
L1 VDDQ6
K9 DQM0
K8 WE#
K7 CAS#
K3 NC5
K2 NC4
K1 DQM1
J9 RAS#
J8 CS#
J7 BA0
J3 A9
J2 CKE
J1 CLK
H9 NC/A11
H8 BA1
H7 NC/A12
Note:
1.
2.
3.
4.
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ML324 ML325
PIN PIN
FILTERED FILTERED
GND GND
FILTERED FILTERED
GND GND
AB2 N1
VCCO VCCO
GND GND
AL2 AA3
FILTERED FILTERED
VCCO VCCO
AH3 E3
AG3 F3
AF3 G3
NC NC
NC NC
AE3 H3
AD3 K3
HEADER HEADER
J49 J166
AB4 L3
AB3 M3
AA4 N3
AG20 AP21
Y3 P3
W4 R3
NC T3
For proper operation of the SDRAM, use the LVCMOSDCI25 voltage standard on the
FPGA pins.
CS# is tied to the jumper labeled RAM_ENABLE/RAM_DISABLE.
Disable the SDRAM when using the DUT pins as standard I/O pins.
For information on SDRAM operation, see:
http://www.micron.com/products/dram/sdram/
www.xilinx.com
Pin Name
D9 VDDQ4
E1 VDDQ5
E2 DQ31
E3 NC1
E7 NC2
E8 DQ16
E9 VSSQ5
F1 VSS2
F2 DQM3
F3 A3
F7 A2
F8 DQM2
F9 VDD2
G1 A4
G2 A5
G3 A6
G7 A10
G8 A0
G9 A1
H1 A7
H2 A8
H3 NC3
Virtex-II Pro ML324 and ML325 Platform
ML324 ML325
PIN PIN
FILTERED FILTERED
VCCO VCCO
FILTERED FILTERED
VCCO VCCO
H2 D1
NC NC
NC NC
V2 M2
FILTERED FILTERED
GND GND
GND GND
P1 U3
N2 D3
P2 G4
R1 H4
VCCO VCCO
P3 J4
N3 L4
R3 M4
T3 N4
U4 T4
V3 U4
V4 V4
W3 W3
NC NC
UG063 (v1.2) May 30, 2006
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