Related Manuals for Xilinx Virtex-II Pro ML324
Summary of Contents for Xilinx Virtex-II Pro ML324
- Page 1 Virtex-II Pro ML324 and ML325 Platform User Guide UG063 (v1.2) May 30, 2006 P/N 0402276-03...
- Page 2 Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
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Page 3: Table Of Contents
Online Document ............6 Virtex-II Pro ML324 and ML325 Platform Package Contents . - Page 4 Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006...
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Page 5: Preface: About This Guide
To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. Conventions This document uses the following conventions. An example illustrates each convention. -
Page 6: Online Document
Virtex-II Red text in another document Platform FPGA User Guide. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... -
Page 7: Virtex-Ii Pro Ml324 And Ml325 Platform
Virtex-II Pro ML324 and ML325 Platform Package Contents • Xilinx Virtex™-II Pro ML324 or ML325 platform (referred to as the “ML32x platform”) • User guide • Four SMA-to-SMA coax cable assemblies • CD-ROM • CompactFlash (CF) memory for System ACE™ solution •... -
Page 8: Conventions
16 or 32 pairs of SMA connectors for the RocketIO transceivers • Power indicator LEDs • General purpose DIP switches, LEDs, and push buttons • 128 Mb SDRAM www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... - Page 9 8 in FF1517 10 in FF1704 * MGT LAUNCH SMA 4 X 4 in FF1517 4 X 5 in FF1704 UG063_01_042706 Figure 1: Virtex-II Pro ML32x Platform Block Diagram Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006...
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Page 10: Detailed Description
ML32x platforms described in this user guide. Each feature is detailed in the numbered sections that follow. UG063_02_042706 Figure 2: Detailed Description of Virtex-II Pro ML32x Platform Components www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... -
Page 11: Power Switch
Appropriate placements of jumpers on these headers enables delivery of all power from either the on-board regulators or power supply jacks marked V5, VCORE, VCCO, VCCAUX, AVCCAUX, VT_TX, VT_RX (top set) and VT_TX, VT_RX (bottom set). Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006... -
Page 12: Power Supply Jacks
When using the flying wire leads or the Parallel Cable IV cable, the System ACE controller will be bypassed, thus causing no disruption in the JTAG chain. 1. For further information, consult the System ACE CompactFlash Solution (DS080) http://www.xilinx.com/bvdocs/publications/ds080.pdf.). www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... -
Page 13: Oscillator Sockets
These connect to the FPGA clock pins as shown in Table Table 5: SMA Clock Pin Connections ML324 ML325 Label Clock Name Clock Name CLK_SMA_TOP CLK_SMA_TOP CLK_SMA_BOT AH20 CLK_SMA_BOT AN21 Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006... -
Page 14: Differential Oscillators
Clock Name Clock Name CLK_BREF_TOP_P CLK_BREF_TOP_P CLK_BREF_TOP_N CLK_BREF_TOP_N CLK_BREF2_BOT_P AK20 CLK_BREF2_BOT_P AT21 CLK_BREF2_BOT_N AL20 CLK_BREF2_BOT_N AU21 CLK_DIFF_TOP_P CLK_DIFF_TOP_P CLK_DIFF_TOP_N CLK_DIFF_TOP_N CLK_DIFF_BOT_P AJ21 CLK_DIFF_BOT_P AN22 CLK_DIFF_BOT_N AH21 CLK_DIFF_BOT_N AP22 www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... -
Page 15: User Leds (Active High)
DS27 AK29 AN12 Table 9: User LEDs - LED Row 2 ML324 ML325 LED ROW 2 DS29 DS28 DS23 AB10 DS16 DS17 DS18 AC11 DS19 DS20 DS21 DS22 Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006... -
Page 16: User Dip Switches (Active High)
Table 10: User DIP Switches - SW1 ML324 ML325 AA10 AB10 AC10 AD10 AE10 AF10 AG10 AH10 AB11 AF11 Table 11: User DIP Switches - SW2 ML324 ML325 www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... -
Page 17: User Push Buttons (Active High)
AB37 AD38 AB36 AD37 AC39 AF40 AC38 AF39 AD34 AG37 AD33 AG38 AD38 AK40 AD37 AK39 AE37 AK36 AE36 AK35 AE39 AM39 AE38 AM38 AF34 AP39 AF33 AP38 Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006... - Page 18 AJ36 AM41 AJ35 AN42 AJ34 AN41 AJ39 AP42 AJ38 AP41 AK36 AT42 AK35 AT41 AK39 AU42 AK38 AU41 AL34 AV42 AL33 AV41 AA37 AL39 AW42 AA36 AL38 AW41 www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006...
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Page 19: Recovered Clock Monitor Headers
ML325 Label J136 J135 J134 AU10 AT12 AT13 AU11 AY15 J140 AU14 AW19 J139 AU15 AV20 J137 AU22 AR23 J138 AU23 AY24 AU29 AY28 J141 AU30 AU30 AN31 Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006... -
Page 20: Program Switch (Active Low)
The open (“O”) position indicates a logic ‘0’ and the closed (“C”) position indicates a logic ‘1’ as shown in Table Table 15: Bitstream Address Table Addr www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... -
Page 21: Rocketio Transceiver Pins
AW32 AW30 AW29 BB32 BB33 BB31 BB30 BB36 BB37 BB35 BB34 AW35 AW36 AW34 AW33 BB40 BB41 BB39 BB38 Note: Shaded areas denote pins that are not used. Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006... -
Page 22: Rs-232 Port Pins
AR26 AR34 R2OUT AM25 AT34 Virtex-II Pro RS-232 T1IN Pin 3 T2IN Pin 7 R1OUT Pin 2 R2OUT Pin 8 UG063_03_042506 Figure 3: RS-232 Pins in DTE Mode www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006... -
Page 23: Sdram Connection
VCCO DQ27 DQ25 DQ14 DQ22 DQ12 DQ20 VSSQ9 FILTERED FILTERED VDDQ3 FILTERED FILTERED VCCO VCCO VDDQ8 FILTERED FILTERED VSSQ4 FILTERED FILTERED VCCO VCCO DQ29 DQ30 DQ17 DQ10 DQ18 Virtex-II Pro ML324 and ML325 Platform www.xilinx.com UG063 (v1.2) May 30, 2006... - Page 24 For information on SDRAM operation, see: http://www.micron.com/products/dram/sdram/ Document status refers to the internal classification of the document. This classification can affect how and to whom the document is distributed. www.xilinx.com Virtex-II Pro ML324 and ML325 Platform UG063 (v1.2) May 30, 2006...