Samsung S3C80M4/F80M4 User Manual page 94

INTERRUPT STRUCTURE
INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 0 to IRQ0, bit 2 to IRQ2, and so on. When the IMR bit of
an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's
IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions
using the Register addressing mode.
5-10
Interrupt Mask Register (IMR)
MSB .7 .6 .5
IRQ5
IRQ6
IRQ7
NOTE: When an interrupt level is masked, any interrupt requests that may be
issued are not recognized by the CPU.
Figure 5-6. Interrupt Mask Register (IMR)
DDH, Set 1, R/W
.4 .3 .2 .1
Reserved
IRQ2
Reserved
IRQ4
Interrupt level enable bits :
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level
S3C80M4/F80M4
.0 LSB
IRQ0