Samsung S3C80M4/F80M4 User Manual page 193

S3C80M4/F80M4
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset
operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too
when the sub-system oscillator is running and watch timer is operating with sub-system clock.
— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/
counters. Idle mode is released by a reset or by an external or internal interrupt.
INT
CLKCON.7
STOP OSC
inst.
STPCON
CLKCON.4-.3
Stop Release
Main-System
fx (fxx)
Oscillator
Circuit
Stop
1/1
Figure 7-4. System Clock Circuit Diagram
1/1-1/4096
Frequency
Dividing
Circuit
1/2 1/8 1/16
Selector
CLOCK CIRCUIT
Basic Timer
Timer/Counter 0
PWM
CPU Clock
IDLE Instruction
7-3