Samsung S3C80M4/F80M4 User Manual page 218

8-BIT PULSE WIDTH MODULATION
8-BIT PULSE WIDTH MODULATION (PWMCON)
The PWM control register, PWMCON is used to select the PWM interrupt to enable or disable the PWM function.
It is located in set 1, bank 0 at address E8H, and is read/write addressable using register addressing mode.
A reset clears PWMCON to "00H". This disable the PWM interrupt, selects an input clock frequency of fosc/64,
disables all PWM interrupt. So, if you want to use the PWM, you must write PWMCON.5 to "1" and write
P0CONH.5-.4 to "10".
To enable the PWM interrupt (IRQ2, vector EAH), you must write PWMCON.2, and PWMCON.1 to "1". To detect
an interrupt pending condition when PWMINT is disabled, the application program polls pending bit, PWMCON.0.
When a "1" is detected, a PWM interrupt is pending. When PWMINT sub-routine has been serviced, the pending
condition must be cleared by software by writing a "0" to the PWM interrupt pending bit, PWMCON.0.
MSB
PWM input clock selection bits:
00 = fosc/64
01 = fosc/8
10 = fosc/2
11 = fosc/1
Not used for the S3C80M4
(must keep always "1")
PWMDATA reload interval Selection bit:
0 = Reload from 8-bit up counter overflow
1 = Reload from 6-bit up counter overflow
12-2
PWM Control Register (PWMCON)
E8H, Set 1, Bank 0, R/W
.7 .6 .5 .4
PWM counter clear bit:
0 = No effect
1 = Clear the PWM counter (when write)
Figure 12-1. PWM Control Register (PWMCON)
.3 .2 .1 .0
PWM overflow interrupt pending bit:
0 = No interrupt pending (when read)
0 = Clear pending bit (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
PWM overflow interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
PWM counter enable bit:
0 = Stop counter
1 = Start counter (Resume countering)
S3C80M4/F80M4
LSB
(8-bit overflow)