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S3C80M4/F80M4
T0CON
— Timer 0 Control Register
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7–.5
.4
.3
.2
.1
.0
NOTE: The T0CON.3 value is automatically cleared to "0" after being cleared counter.
.7
.6
0
0
R/W
R/W
Register addressing mode only
Timer 0 Input Clock Selection Bits
0
0
0
fxx/1024
0
0
1
fxx/256
0
1
0
fxx/64
0
1
1
fxx/8
1
0
0
fxx/1
1
0
1
External clock (T0CLK) falling edge
1
1
0
External clock (T0CLK) rising edge
1
1
1
Counter stop
Not used for the S3C80M4
Timer 0 Counter Clear Bit
0
No effect
1
Clear the timer 0 counter (when write)
Timer 0 Counter Enable Bit
0
Disable counting operation
1
Enable counting operation
Timer 0 Match Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer 0 Interrupt Pending Bit
0
Interrupt request is not pending (when read),
Pending bit clear when write 0
1
Interrupt request is pending (when read)
.5
.4
.3
0
0
0
R/W
R/W
R/W
CONTROL REGISTER
E6H
Set 1, Bank 0
.2
.1
0
0
R/W
R/W
R/W
.0
0
4-25
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