Samsung S3C80M4/F80M4 User Manual page 78

CONTROL REGISTERS
PWMCON
— Pulse Width Modulation Control Register
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7–.6
.5
.4
.3
.2
.1
.0
NOTE: The PWMCON.3 is not automatically cleared to "0". You must pay attention when clear pending bit.
4-20
.7 .6
0 0
R/W R/W
Register addressing mode only
PWM Input Clock Selection Bits
0 0 fosc/64
0 1 fosc/8
1 0 fosc/2
1 1 fosc/1
Not used, But you must keep "1"
PWMDATA Reload Interval Selection Bit
0 Reload from 8-bit up counter overflow
1 Reload from 6-bit up counter overflow
PWM Counter Clear Bit
0 No effect
1 Clear the PWM counter (when write)
PWM Counter Enable Bit
0 Counter STOP
1 Counter RUN (Resume countering)
PWM Overflow Interrupt Enable Bit
0 Disable interrupt
1 Enable interrupt
PWM Overflow Interrupt Pending Bit
0 Interrupt is not pending (when read), Clear pending (when write)
1 Interrupt is pending (when read), No effect (when write)
.5 .4 .3
0 0 0
R/W R/W R/W
S3C80M4/F80M4
E8H Set 1, Bank 0
.2 .1
0 0
R/W R/W R/W
.0
0