Samsung S3C80M4/F80M4 User Manual page 194

CLOCK CIRCUIT
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and
has the following functions:
— Oscillator frequency divide-by value
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If
necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
Oscillator IRQ wake-up function bit:
0 = Enable IRQ for main wake-up in
1 = Diable IRQ for main wake-up
NOTE:
7-4
System Clock Control Register (CLKCON)
MSB .7 .6
Not used for the
S3C80M4
power down mode
in power down mode
After a reset, the slowest clock (divided by 16) is selected as the system clock.
To select faster speeds, load the appropriate values to CLKCON.3 and CLKCON.4.
Figure 7-5. System Clock Control Register (CLKCON)
D4H, Set 1, R/W
.5 .4 .3 .2
Not used for the
S3C80M4
Divide-by selection bits for
CPU clock frequency:
00 = f /16
XX
01 = f /8
XX
10 = f /2
XX
11 = f /1
XX
.1 .0 LSB
S3C80M4/F80M4