Alinx KINTEX-7FPGA User Manual page 22

the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pins of BANK14
respectively. Figure 5-1 shows the hardware connection of QSPI Flash.
QSPI Flash pin assignments:
Signal Name
FPGA_CCLK
FLASH_CE_B
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
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KINTEX-7 FPGA Development Board AX7325B User Manual
Figure 5-1: QSPI Flash Schematic
Figure 5-2: QSPI Flash on the FPGA Board
IO_L6P_T0_FCS_B_14
IO_L1P_T0_D00_MOSI_14
IO_L1N_T0_D01_DIN_14
FPGA Pin Name
CCLK_0
IO_L2P_T0_D02_14
IO_L2N_T0_D03_14
FPGA Pin Number
B10
U19
P24
R25
R20
R21
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