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UM-WI-006
DA16200 H/W Design Guide
low Tx power mode. See
examples of both normal and low Tx power mode in figure xx and figure xx.
The typical output Tx power at 1 Mbps DSSS for each mode is 18.5 dBm in normal Tx power mode
and 9.5 dBm in low Tx power mode. See the datasheet for detailed performance.
2.2.5
VDD_ANA
VDD_ANA is connected to DC-DC output.
2.2.6
VDD_DIG
VDD_DIG is not connected to the power supply but requires 470 nF bypass capacitor.
2.2.7
VDD_FDIO and FDIO_LDO_OUT
VDD_FDIO is connected to VDD of flash memory. This pin can be connected to FDIO_LDO_OUT
when 1.8 V VDD of flash memory is used.
FDIO_LDO_OUT is internal LDO output of the DA16200 for flash memory. The voltage level of
FDIO_LDO_OUT is 1.8 V, so this pin can be used when 1.8 V VDD of flash memory is used.
FDIO_LDO_OUT is turned off in sleep mode to reduce the power consumption.
When 3.3 V VDD of flash memory is used, an additional load switch to control the flash VDD is
needed to reduce the power consumption in sleep mode.
2.2.8
VDD_DIO1 and VDD_DIO2
These are I/O voltage pin of DA16200 and should be same level with I/O voltage of external IC such
as MCU. The DA16200 can support both 1.8 V and 3.3 V of I/O voltage.
2.3
RBIAS
RBIAS (#3 of QFN and #E11 of fcCSP) determine the bias current of DA16200.
1 % tolerance of 30 kΩ of resistor should be adopted to this pin to minimize the variation of current
consumption.
User Manual
CFR0012
Figure 4
below for the VDD connection and refer to the application
Figure 4: High/Low Tx Power Mode Connection
Revision 1.5
13 of 44
NDA Confidential
11-Apr-2022
© 2022 Renesas Electronics
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