Genlock - Tektronix VITS 200 Instruction Manual

Genlock

VITS 200
the black burst channel switch, A3U60 (schematic 6), which switches between
the test signal and ground at the appropriate times.
The Genlock circuitry is located on the Inserter board and is found on the
following schematics: Genlock <4>, Input <5>, and Clocks and Genlock
Offset <6>.
The Program Input is buffered and clamped by A1U42 (schematic 5). The video
then enters the sync stripper IC, A1U44. This IC not only strips off composite
sync but also generates back porch timing for clamping.
Comp sync and back porch timing are level shifted to TTL levels by A1Q1,
A1Q3, A1VR1, and A1VR2 (schematic 5) and gated together by A1U57a and
A1U57b (schematic 5), to get a clamp pulse to control A1U42. A1U44 also
generates a program present signal as long as video greater than 35 dB is present.
The controller, A3U23 (schematic 3), uses this signal to determine whether or
not to try to lock to Program Video or to try to lock to the alternate genlock
source, External 1. The alternate genlock mode must be enabled for this to be
used.
Input buffer A1U42 also drives the analog-to-digital converter (ADC), A1U43
on schematic 5, for the genlock. The ADC has three inputs, two of which are
used. Program Video drives one of the inputs and EXTernal 1 drives the other.
Either can be used by the genlock circuit, as chosen by the controller. The ADC
has an AGC and clamp, with "SYNCTIP" and "BACKPORCH" providing timing.
The clamped and AGC'd video is then routed through an anti-aliasing filter
(A1L1, A1C19, A1C20, and A1C21 on schematic 5) and brought back into the
ADC where it is digitized. The digital output goes into a PAL where it is
inverted and latched. "SIS_TM" from the genlock ASIC (A1U29, schematic 4),
if enabled, holds the same sample across the bottom of sync to block Sound-in-
Sync pulses from reaching the genlock circuitry.
The data then goes to the genlock ASIC (A1U29, schematic 4) which has RAM,
counters, decoders, and other circuitry necessary for genlocking. The composite
sync from the chosen genlock input is also routed to the genlock ASIC through a
PAL (A1U70, schematic 3) and is controlled by the same line that chooses the
genlock input, "GLSEL1". The genlock ASIC uses the comp sync to roughly
position the Horizontal and Vertical Counters within it.
The genlock processor (A1U35, schematic 4), an 8 MHz Z80, uses the data to
calculate the SCH of the incoming video to determine the correct color framing.
It then uses the digitized color subcarrier burst to determine the tangent of the
phase angle between the system clock and the burst. This tangent is used to look
up the arctangent (that is, the angle itself), which is stored in PROM A1U33
Theory of Operation
4–3