Signal and Switching Control
VITS 200
system timing; that is, a clamp pulse derived from the test signal counters. This
is a jumper selection, made with A3J19 (schematic 1) for the EXTernal 1 input.
The external input comp sync is compared to system sync timing pulse
"[SYNCT]" by A3U6A (schematic 1), to check that they are timed close to each
other. "[SYNCT]" is a negative-going 10.8 s pulse which frames the acceptable
time for sync pulses to occur. If any portion of the positive-going external input
comp sync occurs outside of this period, one-shot A3U7A (schematic 1) is
triggered to produce the "BADSYNC1" pulse.
The "BADSYNC1" output is monitored by A3U12 (schematic 6), which does not
allow insertion into Program Video if the "BADSYNC1" pulse occurs. This
protects the program from getting a sync pulse somewhere out in the middle of a
line.
The external input may be changed to DC coupling. This selection is made in
the UTILITIES menu. When this coupling mode is selected, the gate of FET
A3Q1, pulled down to 12V by "DC/[AC1]" for AC coupling, is pulled up to
the level of its source. The FET is then turned on, shorting out the AC-coupling
capacitor, A3C1.
While DC coupled, the external input comp sync is not monitored, nor is
insertion inhibited if sync is not correctly timed. The "CLAMP" pulse to the
input buffer is turned off (A3U55A, A3U56A), and clamp capacitor A3C3 is
shorted to ground by A3U57 on schematic 6. DC coupling of an external input,
then, allows the insertion of signals which do not have sync pulses.
While DC coupled, the DC level may be adjusted with A3R60 When AC
coupled the clamp level may be adjusted with A3R9. A3R15 is used to adjust
the external input gain.
The video from the external input buffer is applied to channel switch A3U41
(schematic 5), which is controlled line-by-line by the signal selection circuitry.
External input channel switch A3U41 drives the program channel switch, A1U64
on schematic 7, which switches between Program Video, VITS signals, and
external input signals.
The Signal and Switching Control circuitry is located on the Controller board
and is found on the following schematics: Microprocessor Kernel <3>, and Test
Signal & Char Sel Memory <4>.
The circuitry for controlling the test signal generator, the external input channel
switch, and the program channel switch resides on both the A3 Controller board
and the A1 Inserter board. The controller (A3U23, schematic 3) stores VITS
selections in RAM (A3U29, schematic 4) which is addressed by the system
Theory of Operation
4–5
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