Tektronix VITS 200 Instruction Manual page 103

Theory of Operation
4–8
The 16 bits can be set or cleared by two sets of DIP switches (A1S5 and A1S6,
schematic 3) accessible through the rear panel of the instrument. The 16 bits are
loaded into two shift registers (A1U22 and A1U23, schematic 3) once every line
by a signal decoded from the Horizontal Counters. The bits are then shifted out
by "IDCLOCK", a clock which is also decoded from the Horizontal Counters.
The serialized ID bits go to A1U15 (schematic 1) where they are gated with
"IDCLOCK" and latched by the eight times subcarrier (8 FSC) clock. If Source
ID is chosen for a certain line, A1U16 (schematic 1) activates "IDEN" which
causes the state machine in A1U15 to be controlled by the latched ID signal.
Character generation begins on the Controller board, A3. Controller A3U23
writes VBI (Vertical Blanking Interval) character selections made from the front
panel or RS-232 into RAM (A3U32, schematic 4) during the vertical sync. The
top 512 bytes contain the 15 different vertical blanking interval messages. Each
vertical message may be up to 23 characters. The lower three blocks of 512
bytes hold three different pages, or frames, of character messages. Each page
may contain 20 characters across by 13 lines down, for a total of 260 characters
per page. In the RAM each character is represented by one byte.
During the vertical blanking interval, P0 and P1 are forced high by "[BLANK]"
(A3U39C and D, schematic 4) to select the block of RAM holding the vertical
interval messages. During the active portion of the picture frame one of the
lower three blocks of data is addressed by CA9 and CA10 from the controller.
Part of the lower nine address bits come from a vertical decoder PROM (A3U37,
schematic 4), and the remainder come from the Horizontal Counters. The
address lines driven by the Horizontal Counters change the character slot in the
RAM as the video scans right over the picture frame. The address lines from the
vertical decoder PROM tell the RAM when a new line of characters is needed.
This addressing is latched by A3U34 (schematic 4) which goes to high imped-
ance when the controller is writing to the RAM.
From the RAM, the bytes, each representing a character, go to the pixel PROM
(A3U31, schematic 4). The pixel PROM contains an array of 32 by 32 pixels for
each character. The pixels are made by serializing 8-bit words out of the pixel
PROM. "BH3" and "BH4" select these four words as the video scans horizontal-
ly. "FLD" takes care of the field interlace. The 16 lines per field per character
are addressed by "DV[0..3]" from vertical decoder PROM A3U37 (schematic
4).
A3U30 (schematic 4) serializes the data. Data is loaded every eight clock cycles
(4 FSC) by "CHLOAD" from A3U35 (schematic 4). A3U30 shifts the pixel data
over to the Inserter board where it is given shaped edges by the state machine
described in the source ID description.
A3U35 (schematic 4) performs several functions besides deriving "CHLOAD"
from the Horizontal Counters. It also looks at the data coming out of the RAM
to determine if a character is being called. If it is, "CHARPRES" is asserted
VITS 200