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6. Programming
Interface
Registers
This chapter contains information needed to write custom software drivers for
the EPC's Flash or SRAM. If using the supplied software that supports Flash
or SRAM as a disk device, skip this chapter. The EPC-26A/27 defines the
following registers in the I/O space.
Bit 7
Bit 6
Device ID Reg
1
1
Config Option Byte 1 Reg
x
x
Low Address Register
Low Order Bits 0-7 of Flash/SRAM Address
Middle Address Register
Low-Middle Bits 8-15 of Flash/SRAM Address
Middle Address Register
High-Middle Bits 16-23 of Flash/SRAM Address
Flash Data Access
SRAM Data Access
Reserved
High Address Register
High Order Bits 24-31 of Flash/SRAM Address
Battery Status
x
x
Figure 8. Flash/SRAM Registers.
The first two registers are standard read/write EXM registers for device
identification and configuration. The EPC-26A/27 responds to accesses to
ports 100h and 102h only if its EXM expansion interface line -EXMID is as-
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
1
1
1
0
x
x
x
x
0
x
x
x
x
x
Bit 0
I/O port
1
100
Cden
102
6
8380
8381
8382
8383
8384
8385
8386
8387
Batt ok
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