Appendix B: Chip Set & I/O Map - RadiSys EPC-26A/27 Manual

Appendix B:
Chip Set & I/O Map
The following defines the I/O addresses decoded by the EPC. It does not define
addresses that might be decoded by EXMs.
First (8-bit) DMA controller:
PicoPower Redwood chip set emulating 8237 of PC/AT
I/O Addr Functional group
000 DMA
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
First Interrupt controller:
PicoPower Redwood chip set emulating 8259 of PC/AT
I/O Addr Functional group
020 Interrupt controller 1
021
I/O Addr Functional group
ED
EC
Usage
Channel 0 address
Channel 0 count
Channel 1 address
Channel 1 count
Channel 2 address
Channel 2 count
Channel 3 address
Channel 3 count
Command/status
DMA request
Command register (R)
Single-bit DMA req mask(W)
Mode
Set byte pointer (R)
Clear byte pointer (W)
Temporary register (R)
Master clear (W)
Clear mode reg counter (R)
Clear all DMA req mask(W)
All DMA request mask
Usage
Port 0
Port 1
82C42 controller:
Usage
Data register
Index register
B
Page B1
B