Watchdog Timer - RadiSys EPC-26A/27 Manual

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EPC-26A/27 Hardware Reference
Software cannot distinguish this from a system with a separate EXM-2A card using
the same configuration. A system cannot enable both the optional Flash/SRAM and
an EXM-2A expansion module at the same time.
Note that the XFORMAT program used to format flash memory is also distributed
with the EXM-2 and EXM-2A expansion modules. Any references to the EXM-2
and/or EXM-2A are intended to denote your flash memory.
Refer to the XFORMAT Software User's Manual for more information about
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formatting SRAM and flash memory.

Watchdog Timer

The watchdog timer is only included with the optional Flash/SRAM. The watchdog
timer is a 16-bit binary counter that monitors for overflow and, when detected, will
signal a watchdog timer event based on the enable bits set in register 815D. The
counter counts with a 64 KHz free running clock. This will cause a watchdog event
after approximately 512 ms if the application software does not reset the timer.
An I/O read to address 815D resets the counter.
Bit 0 of register 815D enables an interrupt if the counter overflows. The clock is
disabled to the counter if the interrupt is pending and not serviced. Service of the
interrupt is signaled to the counter by reading register 815D. This will reset the
counter value and resume counting. The interrupt is signaled on IRQ10.
Bit 1 of register 815D enables a HW reset to occur if the counter overflows. This
reset will reset the entire system. This bit, if set, takes precedence over the setting of
bit 0 in this register.
Application software that utilizes this timer should take care to reset the counter just
prior to enabling either the interrupt or reset bits in register 815D. This will inhibit a
spurious timer event from occurring just after enabling the timer.
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Watchdog Register 815D
7 - 2 1
Unused H/W
Reset
0
IRQ
enable