Intel Agilex 7 FPGA I Series User Manual page 58

Transceiver-soc development kit
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Schematic Signal Name
I2C_QSFPDD800_3V3_SDA
QSFPDD800_TX_P/N[0:3]
QSFPDD800_RX_P/N[0:3]
Four FHT lanes from bank 13A are terminated to MXPM connector (J2).Other lanes
of QSFPDD800 connector is terminated to MXPM connector (J8). For x8
[4:7]
QSFPDD800 topology, 1-1 cable between J2 and J8 need to be used.
Figure 36.
MXPM Cable
FPGA
MXP
MXP port fan out from Intel Agilex 7 FPGA I-Series F-Tile (13A). All four channels can
run up to 32G NRZ and 58G PAM4.
Table 17.
MXP
Schematic Signal Name
FGT_MXPM_TX_P/N_[0:3]
FGT_MXPM_RX_P/N_[0:3]
FMC+ Connector
Intel Agilex 7 I-Series Development Kit supports 2x FMC+ slots for functional
expandability. The x16 FGT lanes from bank 12C and 12A are terminated to FMC-A
(J7) and FMC-B (J9) connectors, respectively. Auxiliary signals are controlled by the
system Intel MAX 10.
SDI Connector
1x FGT channel (13C/Q0/CH3) been terminated to the HD-BNC TX (J1) and RX (J32)
connectors to support up to 12G SDI. System Intel MAX 10 acts as an I
both SDI driver and receiver, along with control signals.
USB Type-C Connector
Intel Agilex 7 I-Series Development Kit has hardware support for the USB Type-C
connector, which supports DP1.4 specification or USB 3.1 functionality through MUX
(TUSB1146). This feature is yet to be validated and implemented.
Serial Buses
SDM I/Os (
bus which communicate with Intel Agilex 7 FPGA core regulators. By default, SDM acts
as SmartVID master and system Intel MAX 10 act as Power GUI master in this chain.
System Intel MAX 10 I/Os (
2
all I
C slave regulator except Intel Agilex 7 FPGA core regulators.
®
Intel Agilex
7 FPGA I-Series Transceiver-SoC Development Kit User Guide
58
MXPM Cable (1-1)
MXPM CONN (J2)
) and Intel MAX 10 I/Os (
SDM_IO0/12
PMB_SDA/SCL
Description
2
I
C data
Transceiver TX
Transceiver RX
85107421
MXPM CONN (J8)
Description
Transceiver TX
Transceiver RX
VCCL_SDA/SCL
) manages the second I
A. Development Kit Components
721605 | 2023.04.10
QSFPDD800 CONN (J22)
2
C master for
) share the same I
2
C bus which access
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2
C

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