Intel Agilex 7 FPGA I Series User Manual page 31

4. Board Test System
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Figure 24. The RDIMMS Tab
The following sections describe controls on this tab.
Start
Initiates DDR4 memory transaction performance analysis.
Stop
Terminates transaction performance analysis.
Reset
Resets transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
• Write and Read performance bars: Show the percentage of maximum
theoretical data rate that the requested transactions are able to achieve.
• Write (MBps) and Read (MBps): Show the number of bytes analyzed per
second.
• Data Bus: 72 bits (8 bits ECC) wide, reference clock is 166.666 MHz, and the
frequency is 1333.33 MHz double data rate 2666.66 MT/s.
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Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
31