Intel Agilex 7 FPGA I Series User Manual page 23

4. Board Test System
721605 | 2023.04.10
• PRBS7: pseudo-random 7-bit binary sequences
• PRBS15: pseudo-random 15-bit binary sequences
• PRBS23: pseudo-random 23-bit binary sequences
• PRBS31: pseudo-random 31-bit binary sequences (default)
Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
• Detected Errors: Displays the number of data errors detected in the received bit
stream.
• Inserted Errors: Displays the number of errors inserted into the transmit data
stream.
• Bit Error Rate: Calculates the bit error rate of the transmit data stream.
• Insert: Insert a one-word error into the transmit data stream each time you click
the button. Insert Error is only enabled during transaction performance analysis.
• Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.
Run Control
• TX and RX performance bars: Show the percentage of maximum theoretical
data rate that the requested transactions are able to achieve.
• Start: This control initiates the loopback tests.
• Data Rate: Displays the XCVR type and data rate of each channel.
Figure 15. QSFPDD NRZ - Data Rate
4.2.5.2. The QSFPDD PAM4 Tab
Similar control functions with the QSFPDD NRZ tab.
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Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
23