Alinx ACU3EG User Manual page 9

ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual
The hardware connection of DDR4 SDRAM on the Pl Side is shown in
Figure 3-2:
Figure 3-2: DDR3 DRAM schematic diagram
PS Side DDR4 DRAM pin assignment:
Signal Name
PS_DDR4_DQS0_P
PS_DDR4_DQS0_N
PS_DDR4_DQS1_P
PS_DDR4_DQS1_N
PS_DDR4_DQS2_P
PS_DDR4_DQS2_N
PS_DDR4_DQS3_P
PS_DDR4_DQS3_N
PS_DDR4_DQS4_P
PS_DDR4_DQS4_N
PS_DDR4_DQS5_P
PS_DDR4_DQS5_N
PS_DDR4_DQS6_P
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Pin Name
PS_DDR_DQS_P0_504
PS_DDR_DQS_N0_504
PS_DDR_DQS_P1_504
PS_DDR_DQS_N1_504
PS_DDR_DQS_P2_504
PS_DDR_DQS_N2_504
PS_DDR_DQS_P3_504
PS_DDR_DQS_N3_504
PS_DDR_DQS_P4_504
PS_DDR_DQS_N4_504
PS_DDR_DQS_P5_504
PS_DDR_DQS_N5_504
PS_DDR_DQS_P6_504
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Pin Number
AF21
AG21
AF23
AG23
AF25
AF26
AE27
AF27
N23
M23
L23
K23
N26