Holtek HT49RU80 Manual page 21

Input/Output Ports
There are two 8-bit bidirectional input/output ports, PA
and PC and one 8-bit input PB and one 7-bit output PD.
PA, PB, PC and PD are mapped to [12H], [14H], [16H]
and [18H] of the RAM, respectively. PA0~PA3 can be
configured as CMOS (output) or NMOS (input/output)
with or without pull-high resistor by options. PA4~PA7
are always pull-high and NMOS (input/output). If NMOS
(input) is chosen, each bit on the port (PA0~PA7) can be
configured as a wake-up input. PB can only be used for
input operation. PC can be configured as CMOS output
or NMOS input/output with or without pull-high resistor
by options. PD can only be used for CMOS output oper-
ation. All the ports for the input operation (PA, PB and
PC), are non-latched, that is, the inputs should be ready
at the T2 rising edge of the instruction ²MOV A, [m]²
(m=12H, 14H or 16H). For PA, PC, PD output operation,
all data are latched and remain unchanged until the out-
put latch is rewritten.
When the PA and PC structures are open drain NMOS
type, it should be noted that, before reading data from
the pads, a ²1² should be written to the related bits to
disable the NMOS device. That is, executing first the in-
struction ²SET [m].i² (i=0~7 for PA) to disable related
NMOS device, and then ²MOV A, [m]² to get stable data.
After a chip reset, these input lines remain at high level
or are left floating (by options). Each bit of these output
latches can be set or cleared by the ²MOV [m], A²
(m=12H or 16H) instruction.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or to the accumulator. When a PA or PC line is
used as an I/O line, the related PA or PC line options
should be configured as NMOS with or without pull-high
resistor. Once a PA or PC line is selected as a CMOS
output, the input function cannot be used.
The input state of a PA or PC line is read from the related
PA or PC pad. When the PA or PC is configured as
NMOS with or without pull-high resistor, one should be
careful when applying a read-modify-write instruction to
PA or PC. Since the read-modify-write will read the en-
tire port state (pads state) first, execute the specified in-
struction and then write the result to the port data
register. When the read operation is executed, a fault
pad state (caused by the load effect or floating state)
may be read. Errors will then occur.
Rev. 1.10
HT49RU80/HT49CU80
There are three function pins that share with the PA port:
PA0/BZ, PA1/BZ and PA3/PFD.
The BZ and BZ are buzzer driving output pair and the
PFD is a programmable frequency divider output. If user
wants to use the BZ/BZ or PFD function, the related PA
port should be set as a CMOS output. The buzzer output
signals are controlled by PA0 and PA1 data registers as
defined in the following table.
PA1 Data PA0 Data
Register Register
0 0
1 0
X 1
Note: ²X² stands for unused
The PFD output signal function is controlled by the PA3
data register and the timer/event counter state. The
PFD output signal frequency is also dependent on the
timer/event counter overflow period. The definitions of
the PFD control signal and PFD output frequency are
listed in the following table.
Timer PA3
Timer Preload Data
Value Register
OFF X
OFF X
ON N
ON N
²X² stands for unused
Note:
²U² stands for unknown
²256² is for TMR0. If TMR1 is used to generate
PFD, the number should be ²65536².
After a chip reset, these input/output lines remain at high
levels (pull-high options) or floating state (non-pull-high
options). It is suggested not to apply the ²read-modify-
write² instructions to the I/O port (since a reading error
may occur). Using ²MOV² instruction to avoid the read-
ing error is suggested. The PB is a 8-bit input port and its
configuration is Schmitt trigger with pull-high resistors.
Each line of PA has the capability of waking-up the de-
vice. The PB0, PB1, PB2, PB3 and PB4 are pin-shared
with INT0, INT1, TMR0, TMR1 and TMR2 input func-
tions, respectively.
21
PA0/PA1 Pad State
PA0=BZ, PA1=BZ
PA0=BZ, PA1=0
PA0=0, PA1=0
PA3
PFD
Pad
Frequency
State
0 U X
1 0 X
f /
INT
0 PFD
[2´(256-N)]
1 0 X
March 2, 2007