Holtek HT49RU80 Manual page 18

ternal selected clock source. Finally, the pulse width
measurement mode can be used to count the high or
low level duration of the external signal (TMR0/TMR1/
TMR2), and the counting is based on the internal se-
lected clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFH (FFFFH). Once an
overflow occurs, the counter is reloaded from the
timer/event counter preload register, and generates an
interrupt request flag (T0F: bit 6 of the INTC0; T1F: bit 4
of the INTC1; T2F: bit 4 of the MFIC).
In the pulse width measurement mode with the values of
the T0ON/T1ON/T2ON and T0E/T1E/T2E bits equal to
²1², after the TMR0/TMR1/TMR2 has received a tran-
sient from low to high (or high to low if the T0E/T1E/T2E
bit is ²0²), it will start counting until the TMR0/TMR1/
TMR2) returns to the original level and resets the
T0ON/T1ON/T2ON. The measured result remains in
the timer/event counter even if the activated transient
occurs again. In other words, only 1-cycle measurement
can be made until the T0ON/T1ON/T2ON is set. The cy-
cle measurement will re-function as long as it receives
further transient pulse. In this operation mode, the
timer/event counter begins counting not according to
the logic level but to the transient edges. In the case of
counter overflows, the counter is reloaded from the
timer/event counter register and issues an interrupt re-
quest, as in the other two modes, i.e., event and timer
modes.
To enable the counting operation, the Timer ON bit
(T0ON/T1ON/T2ON; bit 4 of the TMR0C/TMR1C/
TMR2C) should be set to ²1². In the pulse width mea-
surement mode, the T0ON/T1ON/T2ON is automati-
cally cleared after the measurement cycle is completed.
But in the other two modes, the T0ON/T1ON/T2ON can
only be reset by instructions. The overflow of the
Timer/Event Counter 0/1 is one of the wake-up sources
and can also be applied to a PFD (Programmable Fre-
quency Divider) output at PA3 by options. Only one PFD
(PFD0 or PFD1) can be applied to PA3 by options. No
matter what the operation mode is, writing a 0 to
ET0I/ET1I/ET2I disables the related interrupt service.
When the PFD function is selected, executing ²CLR
[PA].3² instruction to enable PFD output and executing
²SET [PA].3² instruction to disable PFD output.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
Rev. 1.10
HT49RU80/HT49CU80
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1/
TMR2) is read, the clock is blocked to avoid errors, as
this may results in a counting error. Blocking of the clock
should be taken into account by the programmer.
It is strongly recommended to load a desired value into
the TMR0/TMR1/TMR2 register first, before turning on
the related timer/event counter, for proper operation
since the initial value of TMR0/TMR1/TMR2 is un-
known. Due to the timer/event counter scheme, the pro-
grammer should pay special attention on the instruction
to enable then disable the timer for the first time, when-
ever there is a need to use the timer/event counter func-
tion, to avoid unpredictable result. After this procedure,
the timer/event counter function can be operated nor-
mally. The following example is given, using one 8-bit
and one 16-bit width Timer (timer 0; timer 1) cascaded
into 24-bit width.
START:
mov a, 09h ; Set ET0I & EMI bits to
mov intc0, a ; enable Timer 0 and
; global interrupt
mov a, 01h ; Set ET1I bit to enable
mov intc1, a ; Timer 1 interrupt
mov a, 80h ; Set the operating mode as
mov tmr1c, a ; timer mode and select the mask
; option clock source
mov a, 0a0h ; Set the operating mode as timer
mov tmr0c, a ; mode and select the system
; clock/4
set tmr1c.4 ; Enable then disable Timer 1
clr tmr1c.4 ; for the first time
mov a, 00h ; Load a desired value into
mov tmr0, a ; the TMR0/TMR1 register
mov a, 00h ;
mov tmr1l, a ;
mov tmr1h, a ;
set tmr0c.4 ; Normal operating
set tmr1c.4 ;
END
18 March 2, 2007