Holtek HT49RU80 Manual page 11

Bit No. Label
C is set if an operation results in a carry during an addition operation or if a borrow does not
0 C take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
1 AC
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
3 OV
highest-order bit, or vice versa, otherwise OV is cleared.
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
4 PDF
set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
5 TO
set by a WDT time-out.
¾ Unused bit, read as ²0²
6, 7
All interrupts provide a wake-up function. As an interrupt
is serviced, a control transfer occurs by pushing the con-
tents of the program counter onto the stack followed by
a branch to a subroutine at a specified program memory
location. Only the contents of the program counter is
pushed onto the stack. If the contents of the register or
of the status register is altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion on the INT0 or INT1 pins, which will result in their
their related interrupt request flags, EIF0 and EEF1, be-
ing set. After the interrupt is enabled, the stack is not full,
and a high to low transition occurs on the external inter-
rupt pins, a subroutine call to location 04H or 08H occurs.
When the interrupt service routine is serviced, the inter-
rupt request flags, EIF0 and EIF1, and the global enable
bit, EMI, are all cleared to disable other interrupts.
The internal Timer/Event Counter 0 interrupt is
initialised by setting the Timer/Event Counter 0 interrupt
request flag, T0F. This will occur when the timer over-
flows. After the interrupt is enabled, and the stack is not
full, and T0F bit is set, a subroutine call to location 0CH
occurs. The related interrupt request flag, T0F, is reset,
and the EMI bit is cleared to disable further interrupts.
The Timer/Event Counter 1 is operated in the same
manner but its related interrupt request flag is T1F, and
its subroutine call location is 10H.
The UART interrupt is initialised by setting the interrupt
request flag, URF, that is caused by a regular UART re-
ceive signal, caused by a UART transmit signal. After
the interrupt is enabled, the stack is not full, and the URF
bit is set, a subroutine call to location 14H occurs. The
related interrupt request flag, URF, is reset and the EMI
bit is cleared to disable further interrupts.
The multi function interrupt is initialised by setting the in-
terrupt request flag, MFF, that is caused by a regular
internal Timer/Event Counter 2 overflow, caused by a
Rev. 1.10
Function
STATUS (0AH) Register
time base signal or caused by a real time clock signal.
After the interrupt is enabled, the stack is not full, and
the MFF bit is set, a subroutine call to location 18H oc-
curs. The related interrupt request flag, MFF, is reset
and the EMI bit is cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are all held until a ²RETI² in-
struction is executed or the EMI bit and the related inter-
rupt control bit are both set to 1 (if the stack is not full). To
return from the interrupt subroutine a ²RET² or ²RETI²
may be executed. RETI sets the EMI bit and enables an
interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
External interrupt 0
External interrupt 1
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
UART interrupt
Multi function interrupt
(Timer 2, Time base, RTC)
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. It¢s be-
cause interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applica-
tions. During that period, if only one stack is left, and en-
abling the interrupt is not well controlled, operation of the
²call² in the interrupt subroutine may damage the origi-
nal control sequence.
11
HT49RU80/HT49CU80
Priority Vector
1 004H
2 008H
3 00CH
4 010H
5 014H
6 018H
March 2, 2007