Holtek HT49RU80 Manual page 15

Power Down Mode - HALT
The power down mode is initialised when a ²HALT² in-
struction is executed and results in the following.
·
The system oscillator and f
RTC oscillator keeps running, if the WDT oscillator or
the real time clock is selected.
·
The contents of the data memory and registers remain
unchanged.
·
The WDT is cleared and starts recounting, if the WDT
clock source is sourced from the WDT oscillator or the
real time clock oscillator.
·
All I/O ports maintain their original status.
·
The PDF flag is set but the TO flag is cleared.
·
The LCD driver keeps running, if the WDT OSC or
RTC OSC is selected.
The system will exit from power down mode by way of
an external reset, an interrupt, an external falling edge
signal on port A or a WDT overflow. An external reset
causes a device initialisation, while a WDT overflow per-
forms a ²warm reset². After examining the TO and PDF
flags, the reason for a chip reset can be determined. The
PDF flag is cleared by a system power-up or by executing
the ²CLR WDT² instruction, and is set by executing the
²HALT² instruction. However if the TO flag is set and a
WDT time-out occurs, the corresponding wake-up only
resets the program counter and the stack pointer, and
leaves the other registers in their original state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each pin
on port A can be independently selected to wake up the
device using configuration options. Awakening from an
I/O port stimulus, the program resumes execution at the
next instruction. When awakening from an interrupt, two
sequences may occur. If the related interrupt is disabled
or the interrupt is enabled but the stack is full, the pro-
gram resumes execution at the next instruction. But if
the interrupt is enabled, and the stack is not full, the reg-
ular interrupt response takes place.
When an interrupt request flag is set before entering the
power down mode, the system cannot be awakened us-
ing that interrupt.
Rev. 1.10
turn off but the WDT or
SYS
15
HT49RU80/HT49CU80
If a wake-up event occurs, it takes 1024 t
clock periods to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the power down
mode.
Reset
There are three ways in which a reset may occur.
·
RES is reset during normal operation
·
RES is reset during HALT
·
WDT time-out is reset during normal operation
The WDT time-out during a power down differs from
other chip reset conditions, as it will perform only a
²warm reset² that resets only the program counter and
SP and leaves the other circuits in their original state.
Some registers remain unaffected during other reset
conditions. Most registers are reset to their ²initial condi-
tion² once the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish be-
tween different ²chip resets².
TO PDF RESET Conditions
0 0 RES reset during power-on
u u RES reset during normal operation
0 1 RES Wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT Wake-up HALT
Note: ²u² stands for unchanged
W
W
m
Reset Circuit
²*² Make the length of the wiring, which is con-
Note:
nected to the RES pin as short as possible, to
avoid noise interference.
system
SYS
m
March 2, 2007