Holtek HT49RU80 Manual page 10

B a n k 0
B a n k 2
B a n k 3
B a n k 1
RAM Mapping
Rev. 1.10
HT49RU80/HT49CU80
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
·
Arithmetic operations - ADD, ADC, SUB, SBC, DAA
·
Logical operations - AND, OR, XOR, CPL
·
Rotations - RL, RR, RLC, RRC
·
Increment and Decrement - INC, DEC
·
Branch decisions - SZ, SNZ, SIZ, SDZ etc.
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register is 8 bits wide and contains, a carry
flag (C), an auxiliary carry flag (AC), a zero flag (Z), an
overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status reg-
ister can be altered by instructions similar to other reg-
isters. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, device power-on, or
clearing the Watchdog Timer and executing the ²HALT²
instruction. The Z, OV, AC, and C flags reflect the status
of the latest operations.
On entering the interrupt sequence or executing the sub-
routine call, the status register will not be automatically
pushed onto the stack. If the contents of the status is im-
portant, and if the subroutine is likely to corrupt the status
register, precautions should be taken to save it properly.
Interrupts
The device provides two external interrupts, three inter-
nal timer/event counters interrupts, an internal time
base interrupt, an internal real time clock interrupt, and
an UART TX/RX interrupt. The interrupt control register
0, INTC0, and interrupt control register 1, INTC1, both
contain the interrupt control bits that are used to set the
enable/disable status and to record the interrupt request
flags.
Once an interrupt subroutine is serviced, other interrupts
are all blocked, by clearing the EMI bit. This scheme may
prevent any further interrupt nesting. Other interrupt re-
quests may take place during this interval, but only the in-
terrupt request flag will be recorded. If a certain interrupt
requires servicing within the service routine, the EMI bit
and the corresponding bit in the INTC0 or of INTC1 regis-
ter may be set in order to allow interrupt nesting. Once
the stack is full, the interrupt request will not be acknowl-
edged, even if the related interrupt is enabled, until the
SP is decremented. If immediate service is desired, the
stack should be prevented from becoming full.
10 March 2, 2007