Holtek HT49RU80 Manual page 16

Reset Timing Chart
Reset Configuration
To guarantee that the system oscillator is running and
stabilised, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem awakes from the power down mode. After awaken-
ing from the power down mode, an SST delay is added.
An extra option load time delay is added during a reset
and power on.
The functional unit chip reset status is shown below.
Program Counter 000H
Interrupt Disabled
Prescaler Cleared
Cleared. After master reset,
WDT
WDT starts counting
Timer/event Counter Off
Input/output Ports Input mode
Stack Pointer Points to the top of the stack
Timer/Event Counter
Three timer/event counters are implemented in the de-
vice, one 8-bit programmable count-up counter and two
16-bit programmable count-up counter.
The Timer/Event Counter 0 clock source may be
sourced from the system clock, the system clock/4, the
RTC time-out signal or from an external source. The
system clock source or the system clock/4 source is se-
lected by a configuration option.
The Timer/Event Counter 1 clock source may be
sourced from the TMR0 overflow, the system clock, the
time base time-out signal, the system clock/4 or an ex-
ternal source. The three former clock sources are se-
lected by configuration options. Using the external clock
Rev. 1.10
HT49RU80/HT49CU80
input allows external events to be counted, time
intervals or pulse widths to be measured, or an accurate
time base to be generated. Using the internal clock al-
lows an accurate time base to be generated.
The Timer/Event Counter 2 contains a 16-bit program-
mable count-up counter whose clock may be sourced
from an external source or an internal clock source. The
internal clock source comes from f
clock input allows the user to count external events,
measure time intervals or pulse widths, or to generate
an accurate time base.
There are two registers related to the Timer/Event
Counter 0; TMR0 and TMR0C. Two physical registers
are mapped to the TMR0 location. Writing to TMR0
places the starting value in the Timer/Event Counter 0
register while reading TMR0 takes the contents of the
Timer/Event Counter 0. The TMR0C register is a
timer/event counter control register, which defines the
timer options.
There are three registers related to the Timer/Event
Counter 1; TMR1H, TMR1L and TMR1C. Writing to
TMR1L will only transfer the data into an internal
lower-order byte buffer (8-bit) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L registers,
respectively. The Timer/Event Counter 1 preload regis-
ter is changed by each writing TRM1H operations.
Reading TMR1H will latch the contents of TMR1H and
TMR1L counters to the destination and the lower-order
byte buffer, respectively. Reading the TMR1L will read
the contents of the lower-order byte buffer. The TMR1C
is the Timer/Event Counter 1 control register, which de-
fines the operating mode, counting enable or disable
and an active edge.
There are three registers related to the Timer/Event
Counter 2; TMR2H (20H), TMR2L (21H), TMR2C (22H).
Writing TMR2L will only place the written data to an in-
ternal lower-order byte buffer (8-bit) and writing TMR2H
will transfer the specified data and the contents of the
lower-order byte buffer to TMR2H and TMR2L registers,
respectively. The Timer/Event Counter 2 preload regis-
ter is changed by each writing TRM2H operations.
Reading TMR2H will latch the contents of the TMR2H
and TMR2L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR2L will read the contents of the lower-order byte
buffer. The TMR2C is the Timer/Event Counter 2 control
register, which defines the operating mode, counting en-
able or disable and an active edge.
The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) and
T2M0, T2M1 (TMR2C) bits define the operation mode.
The event count mode is used to count external events,
which means that the clock source is from an external
(TMR0/TMR1/TMR2) pin. The timer mode functions as
a normal timer with the clock source coming from the in-
16
/4. The external
SYS
March 2, 2007