Supermicro X12DPFR-AN6 User Manual page 78

Super X12DPFR-AN6 User's Manual
Memory RAS Configuration Setup

Use this submenu to configure the following Memory RAS (Reliability_Availability_Ser-
viceability) settings.
Enable Pcode WA (Workaround) for SAI (Security Attribute of the Initiator) PG
(Policy Group)
Pcode, a register transfer language designed for reverse engineering, translates indi-
vidual processor instructions into a sequence of Pcode operations in order to facilitate
the construction of data-flow graphs and dissembling of processor instructions for ma-
chine application. Select Enabled to allow Pcode to work around the SAI group policy to
achieve a solution with a next-step instruction. The options are Disabled and Enabled.
Mirror Mode (Unavailable when "UEFI ARM Mirror" below is set to Enabled and
"ADDDC Sparing" below is set to Disabled)
Use this feature to configure the mirror mode settings for all 1LM/2LM memory modules
installed in the system which will create a duplicate copy of data stored in the memory to
increase memory security, but it will reduce the memory capacity into half. The options
are Disabled, Full Mirror Mode and Partial Mirror Mode.
UEFI ARM Mirror (Only available when "Mirror Mode" is set to Disabled and
"ADDDC Sparing" is set to Disabled)
Select Enabled to mimic behavior of UEFI-based ARM (Address Range Mirror) with setup
options to increase memory security, but it will reduce the memory capacity into half. The
options are Disabled and Enabled.
Correctable Error Threshold
This feature allows the user to enter the threshold value for correctable memory errors.
The default setting is 512.
Partial Cache Line Sparing (PCLS)
Select Enabled to support partial cache line sparing, which will allow partial of data con-
tained in a cache line to be copied in the cache memory for safe-keeping/data security.
The options are Disabled and Enabled.
ADDDC (Adaptive Double Device Data Correction) Sparing (Available if "UEFI
ARM Mirror" is set to Enabled)
Select Enable for Adaptive Double Device Data Correction (ADDDC) support, which will
not only provide memory error checking and correction but will also prevent the system
from issuing a performance penalty before a device fails. Please note that virtual lock-
step mode will only start to work for ADDDC after a faulty DRAM module is spared. The
options are Enabled and Disabled.
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