u-blox LARA-R203 System Integration Manual page 150

SARA-U2
Pin No Pin Name Description
2
26 SDA I
1.8 V, open drain
Driver strength: 1 mA
27 SCL I 2
1.8 V, open drain
Driver strength: 1 mA
28 USB_D- USB Data I/O (D-)
High-Speed USB 2.0
29 USB_D+ USB Data I/O (D+)
High-Speed USB 2.0
30 GND Ground
31 RSVD Reserved
32 GND Ground
33 RSVD Reserved
To be externally connected to GND
34 I2S_WA I 2
1.8 V, Driver strength: 2 mA
35 I2S_TXD I 2
1.8 V, Driver strength: 2 mA
2
36 I2S_CLK I
1.8 V, Driver strength: 2 mA
2
37 I2S_RXD I
1.8 V, Inner pull-down: ~9 k
38 SIM_CLK SIM Clock Output
39 SIM_IO SIM Data I/O
40 SIM_RST SIM Reset Output
41 VSIM SIM Supply Output
42 SIM_DET 1.8V SIM Detection
43 GND Ground
44 RSVD Reserved
45 RSVD Reserved
46 RSVD Reserved
47 RSVD Reserved
48 RSVD Reserved
49 RSVD Reserved
50 GND Ground
51-53 VCC Module Supply Input
54-55 GND Ground
56 ANT RF Antenna Input/Output
57-58 GND Ground
59 GND Ground
60-61 GND Ground
62 ANT_DET Antenna Detection Input
63-96 GND Ground
97-98 - Not Available
99 - Not Available
100 - Not Available
Table 54: SARA-U2 and LARA-R2 series modules pin assignment with remarks for migration
For further details regarding the characteristics, capabilities, usage or settings applicable for each interface of the
SARA-U2 and LARA-R2 series modules, see the LARA-R2 series Data Sheet [1], the SARA-U2 series Data Sheet [27],
the SARA-G3 / SARA-U2 series System Integration Manual [28], the u-blox AT Commands Manual [2] and the
Nested Design Application Note [26].
24 Not supported by LARA-R204-02B and LARA-R220-62B modules product versions.
25 Not supported by "02" and "62" product versions.
UBX-16010573 - R12
C Data I/O
C Clock Output
S Word Alignment I/O, or GPIO
S Data Output, or GPIO
S Clock I/O, or GPIO
S Data Input, or GPIO
Normal range: 3.3 V – 4.4 V
Extended range: 3.1 V – 4.5 V
LARA-R2 series - System Integration Manual
LARA-R2
Pin Name Description
2
SDA I C Data I/O
1.8 V, open drain
Driver strength: 1 mA
SCL I 2 C Clock Output
1.8 V, open drain
Driver strength: 1 mA
USB_D- USB Data I/O (D-)
High-Speed USB 2.0
USB_D+ USB Data I/O (D+)
High-Speed USB 2.0
GND Ground
RSVD Reserved
GND Ground
RSVD Reserved
To be externally connected to GND
I2S_WA I 2 S Word Alignment I/O
1.8 V, Driver strength: 6 mA
I2S_TXD I 2 S Data Output
1.8 V, Driver strength: 6 mA
2 24
I2S_CLK I S Clock I/O , or GPIO
1.8 V, Driver strength: 6 mA
2 24
I2S_RXD I S Data Input
1.8 V, Inner pull-down: ~7.5 k
SIM_CLK SIM Clock Output
SIM_IO SIM Data I/O
SIM_RST SIM Reset Output
VSIM SIM Supply Output
SIM_DET 1.8 V GPIO settable as SIM Detection
GND Ground
SDIO_D2 1.8 V, SDIO serial data [2]
SDIO_CLK 1.8 V, SDIO serial clock
SDIO_CMD 1.8 V, SDIO command
SDIO_D0 1.8 V, SDIO serial data [0]
SDIO_D3 1.8 V, SDIO serial data [3]
SDIO_D1 1.8 V, SDIO serial data [1]
GND Ground
VCC Module Supply Input
Normal range: 3.3 V – 4.4 V
Extended range: 3.0 V – 4.5 V
GND Ground
ANT1 RF Antenna Input/Output (primary)
GND Ground
ANT_DET Antenna Detection Input
GND Ground
ANT2 RF Antenna Input (secondary)
GND Ground
RSVD Reserved
HSIC_DATA HSIC USB data line
HSIC_STRB HSIC USB strobe line
Remarks for migration
No functional difference
No functional difference
No functional difference
No functional difference
No functional difference
No functional difference
24 , or GPIO No functional difference
24 , or GPIO No functional difference
No functional difference
, or GPIO No functional difference
No functional difference
No functional difference
No functional difference
No functional difference
No functional difference
25 RSVD  SDIO
25 RSVD  SDIO
25
RSVD  SDIO
25
RSVD  SDIO
25 RSVD  SDIO
25 RSVD  SDIO
No functional difference
Larger range for LARA-R2
No functional difference
GND  ANT_DET
ANT_DET  ANT2
No functional difference
25
Not Available  HSIC
25
Not Available  HSIC
Page 150 of 157
Appendix